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petechouigcbot
petechou
authored and
igcbot
committed
vISA: Add MTL target.
Add MTL target.
1 parent c6a01f3 commit 20ef9c5

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12 files changed

+50
-16
lines changed

12 files changed

+50
-16
lines changed

‎visa/BinaryEncodingIGA.cpp

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -344,6 +344,7 @@ Platform BinaryEncodingIGA::getIGAInternalPlatform(TARGET_PLATFORM genxPlatform)
344344
platform = Platform::XE_HP;
345345
break;
346346
case Xe_DG2:
347+
case Xe_MTL:
347348
platform = Platform::XE_HPG;
348349
break;
349350
case Xe_PVC:
@@ -1943,6 +1944,8 @@ SWSB_ENCODE_MODE vISA::GetIGASWSBEncodeMode(const IR_Builder& builder) {
19431944
return SWSB_ENCODE_MODE::SWSBInvalidMode;
19441945

19451946
if (builder.hasThreeALUPipes()) {
1947+
if (builder.getPlatform() == Xe_MTL)
1948+
return SWSB_ENCODE_MODE::ThreeDistPipeDPMath;
19461949
return SWSB_ENCODE_MODE::ThreeDistPipe;
19471950
}
19481951
else if (builder.hasFourALUPipes()) {

‎visa/G4_IR.cpp

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -950,6 +950,11 @@ bool G4_INST::isMathPipeInst() const
950950
return true;
951951
}
952952

953+
if (isDFInstruction())
954+
{
955+
if (builder.getPlatform() == Xe_MTL)
956+
return true;
957+
}
953958

954959
return false;
955960
}

‎visa/G4_Kernel.cpp

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -839,6 +839,7 @@ static iga_gen_t getIGAPlatform(TARGET_PLATFORM genPlatform)
839839
case GENX_TGLLP:platform = IGA_GEN12p1; break;
840840
case Xe_XeHPSDV: platform = IGA_XE_HP; break;
841841
case Xe_DG2:
842+
case Xe_MTL:
842843
platform = IGA_XE_HPG;
843844
break;
844845
case Xe_PVC:
@@ -1031,6 +1032,7 @@ void G4_Kernel::setKernelParameters()
10311032
{
10321033
case Xe_XeHPSDV:
10331034
case Xe_DG2:
1035+
case Xe_MTL:
10341036
switch (overrideNumThreads)
10351037
{
10361038
case 4:
@@ -1154,6 +1156,7 @@ void G4_Kernel::setKernelParameters()
11541156
{
11551157
case Xe_XeHPSDV:
11561158
case Xe_DG2:
1159+
case Xe_MTL:
11571160
switch (overrideNumThreads)
11581161
{
11591162
case 4:
@@ -1196,6 +1199,7 @@ void G4_Kernel::setKernelParameters()
11961199
{
11971200
case Xe_XeHPSDV:
11981201
case Xe_DG2:
1202+
case Xe_MTL:
11991203
case Xe_PVC:
12001204
case Xe_PVCXT:
12011205
numAcc = 4;
@@ -1222,6 +1226,7 @@ void G4_Kernel::setKernelParameters()
12221226
{
12231227
case Xe_XeHPSDV:
12241228
case Xe_DG2:
1229+
case Xe_MTL:
12251230
switch (numRegTotal)
12261231
{
12271232
case 256:

‎visa/HWCaps.inc

Lines changed: 22 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -513,7 +513,8 @@ SPDX-License-Identifier: MIT
513513

514514
bool noInt64() const
515515
{
516-
return getPlatform() == GENX_ICLLP || isXeLP() || getPlatform() == Xe_DG2;
516+
return getPlatform() == GENX_ICLLP || isXeLP() || getPlatform() == Xe_DG2 ||
517+
getPlatform() == Xe_MTL;
517518
}
518519

519520
bool noFP64() const
@@ -524,7 +525,8 @@ SPDX-License-Identifier: MIT
524525
bool no64bitRegioning() const
525526
{
526527
return getPlatform() == GENX_CHV || getPlatform() == GENX_BXT ||
527-
getPlatform() == GENX_ICLLP || isXeLP() || getPlatform() == Xe_DG2;
528+
getPlatform() == GENX_ICLLP || isXeLP() ||
529+
getPlatform() == Xe_DG2 || getPlatform() == Xe_MTL;
528530
}
529531

530532
bool hasBankCollision() const
@@ -539,12 +541,15 @@ SPDX-License-Identifier: MIT
539541

540542
bool oneGRFBankDivision() const
541543
{
542-
return getPlatform() != Xe_XeHPSDV && getPlatform() != Xe_DG2 && !(getPlatform() == Xe_PVC && !getOption(vISA_HasPartialInt64));
544+
return getPlatform() != Xe_XeHPSDV && getPlatform() != Xe_DG2 &&
545+
getPlatform() != Xe_MTL &&
546+
!(getPlatform() == Xe_PVC && !getOption(vISA_HasPartialInt64));
543547
}
544548

545549
bool hasMadm() const
546550
{
547-
return getPlatform() != GENX_ICLLP && !isXeLP() && getPlatform() != Xe_DG2;
551+
return getPlatform() != GENX_ICLLP && !isXeLP() &&
552+
getPlatform() != Xe_DG2 && getPlatform() != Xe_MTL;
548553
}
549554

550555
bool hasSIMD16TypedRW() const
@@ -638,7 +643,7 @@ SPDX-License-Identifier: MIT
638643
{
639644
return 16;
640645
}
641-
else if (plat == Xe_XeHPSDV || plat == Xe_DG2)
646+
else if (plat == Xe_XeHPSDV || plat == Xe_DG2 || plat == Xe_MTL)
642647
{
643648
return 8;
644649
}
@@ -746,7 +751,7 @@ SPDX-License-Identifier: MIT
746751

747752
bool hasFP64Acc() const
748753
{
749-
return !noFP64();
754+
return !noFP64() && getPlatform() != Xe_MTL;
750755
}
751756

752757
bool hasMathAcc() const
@@ -829,13 +834,15 @@ SPDX-License-Identifier: MIT
829834
bool hasTwoGRFBank16Bundles() const
830835
{
831836
const TARGET_PLATFORM P = getPlatform();
832-
return P == Xe_XeHPSDV || P == Xe_DG2 || (P == Xe_PVC && !getOption(vISA_HasPartialInt64));
837+
return P == Xe_XeHPSDV || P == Xe_DG2 || P == Xe_MTL ||
838+
(P == Xe_PVC && !getOption(vISA_HasPartialInt64));
833839
}
834840

835841
bool hasOneGRFBank16Bundles() const
836842
{
837843
const TARGET_PLATFORM P = getPlatform();
838-
return P != Xe_XeHPSDV && P != Xe_DG2 && !(P == Xe_PVC && !getOption(vISA_HasPartialInt64));
844+
return P != Xe_XeHPSDV && P != Xe_DG2 && P != Xe_MTL &&
845+
!(P == Xe_PVC && !getOption(vISA_HasPartialInt64));
839846
}
840847

841848
bool hasDPASSrc0Src1BankConflict() const
@@ -850,7 +857,7 @@ SPDX-License-Identifier: MIT
850857

851858
bool hasDPAS() const
852859
{
853-
return getPlatform() >= Xe_XeHPSDV;
860+
return getPlatform() >= Xe_XeHPSDV && getPlatform() != Xe_MTL;
854861
}
855862

856863
bool hasAMFSFastClear() const
@@ -877,7 +884,7 @@ SPDX-License-Identifier: MIT
877884
bool hasThreeALUPipes() const
878885
{
879886
const TARGET_PLATFORM P = getPlatform();
880-
return (P == Xe_XeHPSDV || P == Xe_DG2);
887+
return (P == Xe_XeHPSDV || P == Xe_DG2 || P == Xe_MTL);
881888
}
882889

883890
bool hasFusedEUWA() const
@@ -888,7 +895,8 @@ SPDX-License-Identifier: MIT
888895

889896
bool hasFusedEU() const
890897
{
891-
return (getPlatform() == GENX_TGLLP || getPlatform() == Xe_XeHPSDV || getPlatform() == Xe_DG2);
898+
return (getPlatform() == GENX_TGLLP || getPlatform() == Xe_XeHPSDV ||
899+
getPlatform() == Xe_DG2 || getPlatform() == Xe_MTL);
892900
}
893901

894902
bool hasFusedEUNoMaskWA() const
@@ -906,7 +914,7 @@ SPDX-License-Identifier: MIT
906914

907915
bool hasSLMWARIssue() const
908916
{
909-
return getPlatform() == Xe_DG2 || getPlatform() == Xe_PVC || getPlatform() == Xe_PVCXT;
917+
return getPlatform() == Xe_DG2 || getPlatform() == Xe_MTL || getPlatform() == Xe_PVC || getPlatform() == Xe_PVCXT;
910918
}
911919

912920
bool hasLongOperandTypeDepIssue() const
@@ -1023,7 +1031,8 @@ SPDX-License-Identifier: MIT
10231031

10241032
bool hasA0WARHWissue()
10251033
{
1026-
return (getPlatform() == Xe_XeHPSDV || getPlatform() == Xe_DG2 || getPlatform() == Xe_PVC);
1034+
return (getPlatform() == Xe_XeHPSDV || getPlatform() == Xe_DG2 ||
1035+
getPlatform() == Xe_MTL || getPlatform() == Xe_PVC);
10271036
}
10281037

10291038
bool hasFtoPackedHFMove() const

‎visa/IsaVerification.cpp

Lines changed: 4 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1835,8 +1835,10 @@ void vISAVerifier::verifyInstructionArith(
18351835

18361836
// check for IEEE macros support
18371837
// !hasMadm() check
1838-
bool noMadm = (platform == GENX_ICLLP || platform == GENX_TGLLP);
1839-
noMadm |= platform == Xe_DG2;
1838+
bool noMadm = platform == GENX_ICLLP ||
1839+
platform == GENX_TGLLP ||
1840+
platform == Xe_DG2 ||
1841+
platform == Xe_MTL;
18401842
if (noMadm)
18411843
{
18421844
bool fOpcodeIEEE = (opcode == ISA_DIVM) || (opcode == ISA_SQRTM);

‎visa/LocalScheduler/G4_Sched.cpp

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -637,6 +637,7 @@ GRFMode::GRFMode(TARGET_PLATFORM platform)
637637
case Xe_DG2:
638638
case Xe_PVC:
639639
case Xe_PVCXT:
640+
case Xe_MTL:
640641
configurations.resize(2);
641642
// Configurations for this platform <GRF, numThreads>
642643
configurations[0] = std::make_pair(128, 8);

‎visa/VisaToG4/TranslateSendLdStLsc.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -16,7 +16,7 @@ using namespace vISA;
1616
G4_ExecSize IR_Builder::lscMinExecSize(LSC_SFID lscSfid) const
1717
{
1818
const TARGET_PLATFORM P = getPlatform();
19-
uint32_t minExecSize = (P == Xe_DG2 ? 8 : 16);
19+
uint32_t minExecSize = ((P == Xe_DG2 || P == Xe_MTL) ? 8 : 16);
2020
if (!hasLSCEnableHalfSIMD())
2121
{
2222
minExecSize *= 2;

‎visa/common.cpp

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -31,6 +31,8 @@ const PlatformInfo PlatformInfo::ALL_PLATFORMS[] = {
3131
"XeHP_SDV"),
3232
PlatformInfo(Xe_DG2, PlatformGen::XE, 13, 32,
3333
"DG2"),
34+
PlatformInfo(Xe_MTL, PlatformGen::XE, 13, 32,
35+
"MTL"),
3436
PlatformInfo(Xe_PVC, PlatformGen::XE, 14, 64,
3537
"PVC"),
3638
PlatformInfo(Xe_PVCXT, PlatformGen::XE, 15, 64,

‎visa/iga/IGALibrary/IR/Instruction.cpp

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -176,6 +176,9 @@ SWSB::InstType Instruction::getSWSBInstType(SWSB_ENCODE_MODE mode) const {
176176
if (is(Op::MATH))
177177
return SWSB::InstType::MATH;
178178

179+
// instruction with any of operand type is DF belongs to Math pipe
180+
if (mode == SWSB_ENCODE_MODE::ThreeDistPipeDPMath && isDF())
181+
return SWSB::InstType::MATH;
179182

180183
if (getOpSpec().isDpasFamily()) {
181184
return SWSB::InstType::DPAS;

‎visa/iga/IGALibrary/Models/Models.hpp

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -393,6 +393,8 @@ namespace iga
393393
case SWSB_ENCODE_MODE::ThreeDistPipe:
394394
return 16;
395395

396+
case SWSB_ENCODE_MODE::ThreeDistPipeDPMath:
397+
return 16;
396398
case SWSB_ENCODE_MODE::FourDistPipe:
397399
case SWSB_ENCODE_MODE::FourDistPipeReduction:
398400
return 32;

‎visa/iga/IGALibrary/api/iga_types_swsb.hpp

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -31,6 +31,7 @@ namespace iga
3131
ThreeDistPipe = 2, // XeHP/XeHPG: 3 distance pipe
3232
FourDistPipe = 3, // XeHPC (early variant): 4 distance pipes
3333
FourDistPipeReduction = 6, // XeHPC variation: 4 distance pipes with Long pipe reduction
34+
ThreeDistPipeDPMath = 7, // MTL: 3 distance pipe with DP operations in Math pipe
3435

3536
};
3637

‎visa/include/visa_igc_common_header.h

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -484,6 +484,7 @@ typedef enum {
484484
GENX_TGLLP,
485485
Xe_XeHPSDV,
486486
Xe_DG2,
487+
Xe_MTL,
487488
Xe_PVC,
488489
Xe_PVCXT,
489490
ALL

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