Implement predicated load/store

- Implement GenISA predicated load and store intrinsics
- Implement pass which promotes llvm load and store to predicated GenISA
  load/store intrinsics

Author: YuriPlyakhin

IGC/AdaptorOCL/UnifyIROCL.cpp

@@ -131,6 +131,7 @@ SPDX-License-Identifier: MIT
 #include "Compiler/Optimizer/OpenCLPasses/MinimumValidAddressChecking/MinimumValidAddressChecking.hpp"
 #include "Compiler/Optimizer/OpenCLPasses/Spv2dBlockIOResolution/Spv2dBlockIOResolution.hpp"
 #include "Compiler/Optimizer/OpenCLPasses/SpvSubgroupMMAResolution/SpvSubgroupMMAResolution.hpp"
+#include "Compiler/Optimizer/PromoteToPredicatedMemoryAccess.hpp"
 
 #include "common/debug/Debug.hpp"
 #include "common/igc_regkeys.hpp"
@@ -640,6 +641,12 @@ static void CommonOCLBasedPasses(OpenCLProgramContext* pContext)
 
     mpm.add(new ScalarArgAsPointerAnalysis());
 
+    // Inserting Predicated Load If Conversion pass before OCL Scalaraizer to simplify pattern matching for the pass
+    if (IGC_IS_FLAG_ENABLED(EnablePromoteToPredicatedMemoryAccess))
+    {
+        mpm.add(new PromoteToPredicatedMemoryAccess());
+    }
+
     if (IGC_IS_FLAG_DISABLED(DisableOCLScalarizer))
     {
         mpm.add(createScalarizerPass(SelectiveScalarizer::Auto));

IGC/Compiler/CISACodeGen/CShader.cpp

@@ -4201,15 +4201,24 @@ Tristate CShader::shouldGenerateLSCQuery(
         return Tristate::False;
     }
 
-    // Geneate LSC for load/store instructions as Load/store emit can
+    // Generate LSC for load/store instructions as Load/store emit can
     // handle full-payload uniform non-transpose LSC on PVC A0.
     if (vectorLdStInst == nullptr
         || isa<LoadInst>(vectorLdStInst)
         || isa<StoreInst>(vectorLdStInst))
         return Tristate::True;
-    // special checks for typed r/w
+
     if (GenIntrinsicInst* inst = dyn_cast<GenIntrinsicInst>(vectorLdStInst))
     {
+        // Generate LSC for predicated load/store instructions similar to
+        // simple load/store instructions.
+        if (inst->getIntrinsicID() == GenISAIntrinsic::GenISA_PredicatedLoad ||
+            inst->getIntrinsicID() == GenISAIntrinsic::GenISA_PredicatedStore)
+        {
+            return Tristate::True;
+        }
+
+        // special checks for typed r/w
         if (inst->getIntrinsicID() == GenISAIntrinsic::GenISA_typedread ||
             inst->getIntrinsicID() == GenISAIntrinsic::GenISA_typedwrite ||
             inst->getIntrinsicID() == GenISAIntrinsic::GenISA_typedwriteMS ||