Enable legacy memory intrinsic translation by default

mshelego · igcbot · commit 23a0bdc3db2f · 2024-07-29T17:07:46.000+02:00
.
diff --git a/IGC/VectorCompiler/lib/GenXCodeGen/GenX.td b/IGC/VectorCompiler/lib/GenXCodeGen/GenX.td
@@ -383,6 +383,7 @@ def : Proc<"XeHPG", [
   FeatureMultiIndirectByteRegioning,
   FeatureSLM128K,
   FeatureThreadPayloadInMemory,
+  FeatureTransLegacy,
 ]>;
 
 def : Proc<"XeLPG", [
@@ -404,6 +405,7 @@ def : Proc<"XeLPG", [
   FeatureMultiIndirectByteRegioning,
   FeatureSLM128K,
   FeatureThreadPayloadInMemory,
+  FeatureTransLegacy,
 ]>;
 
 def : Proc<"XeLPGPlus", [
@@ -425,6 +427,7 @@ def : Proc<"XeLPGPlus", [
   FeatureMultiIndirectByteRegioning,
   FeatureSLM128K,
   FeatureThreadPayloadInMemory,
+  FeatureTransLegacy,
 ]>;
 
 def : Proc<"XeHPC", [
@@ -451,6 +454,7 @@ def : Proc<"XeHPC", [
   FeatureSLM128K,
   FeatureSwitchjmp,
   FeatureThreadPayloadInMemory,
+  FeatureTransLegacy,
 ]>;
 
 def : Proc<"XeHPCVG", [
@@ -477,6 +481,7 @@ def : Proc<"XeHPCVG", [
   FeatureSLM128K,
   FeatureSwitchjmp,
   FeatureThreadPayloadInMemory,
+  FeatureTransLegacy,
 ]>;
 
 def : Proc<"Xe2", [
diff --git a/IGC/VectorCompiler/test/CisaBuilder/math_f16.ll b/IGC/VectorCompiler/test/CisaBuilder/math_f16.ll
@@ -1,6 +1,6 @@
 ;=========================== begin_copyright_notice ============================
 ;
-; Copyright (C) 2023 Intel Corporation
+; Copyright (C) 2023-2024 Intel Corporation
 ;
 ; SPDX-License-Identifier: MIT
 ;
@@ -14,6 +14,7 @@
 
 ; COM: ;;;;;;;;;; CHECKERS ;;;;;;;;;;
 
+; CHECK: .decl  {{V[^ ]+}} v_type=G type=hf num_elts=8
 ; CHECK: .decl  [[SRC:V[^ ]+]] v_type=G type=hf num_elts=8
 ; CHECK: cos (M1, 8) [[COS:V[^ ]+]](0,0)<1> [[SRC]](0,0)<1;1,0>
 ; CHECK: exp (M1, 8) [[EXP:V[^ ]+]](0,0)<1> [[SRC]](0,0)<1;1,0>
diff --git a/IGC/VectorCompiler/test/CisaBuilder/math_f32.ll b/IGC/VectorCompiler/test/CisaBuilder/math_f32.ll
@@ -1,6 +1,6 @@
 ;=========================== begin_copyright_notice ============================
 ;
-; Copyright (C) 2023 Intel Corporation
+; Copyright (C) 2023-2024 Intel Corporation
 ;
 ; SPDX-License-Identifier: MIT
 ;
@@ -14,6 +14,7 @@
 
 ; COM: ;;;;;;;;;; CHECKERS ;;;;;;;;;;
 
+; CHECK: .decl  {{V[^ ]+}} v_type=G type=f num_elts=8
 ; CHECK: .decl  [[SRC:V[^ ]+]] v_type=G type=f num_elts=8
 ; CHECK: cos (M1, 8) [[COS:V[^ ]+]](0,0)<1> [[SRC]](0,0)<1;1,0>
 ; CHECK: exp (M1, 8) [[EXP:V[^ ]+]](0,0)<1> [[SRC]](0,0)<1;1,0>
diff --git a/IGC/VectorCompiler/test/CisaBuilder/rdtsc.ll b/IGC/VectorCompiler/test/CisaBuilder/rdtsc.ll
@@ -14,19 +14,22 @@
 
 ; COM: ;;;;;;;;;; CHECKERS ;;;;;;;;;;
 
+; CHECK: .decl [[SURF:V[^ ]+]] v_type=G type=d num_elts=1 align=dword
 ; CHECK: .decl [[TMC_1:V[^ ]+]] v_type=G type=q num_elts=1 align=qword
 ; CHECK: .decl [[TMC_2:V[^ ]+]] v_type=G type=q num_elts=1 align=qword
 ; CHECK: .decl [[RES:V[^ ]+]] v_type=G type=d num_elts=8 align=GRF
+; CHECK: .decl [[ALIAS_SURF:V[^ ]+]] v_type=G type=ud num_elts=1 alias=<[[SURF]], 0>
 ; CHECK: .decl [[ALIAS_1:V[^ ]+]] v_type=G type=d num_elts=2 alias=<[[TMC_1]], 0>
 ; CHECK: .decl [[ALIAS_2:V[^ ]+]] v_type=G type=d num_elts=2 alias=<[[TMC_2]], 0>
 ; CHECK: .decl [[ALIAS_RES:V[^ ]+]] v_type=G type=q num_elts=4 alias=<[[RES]], 0>
 ; CHECK: .decl [[SURFACE:T[^ ]+]] v_type=T num_elts=1
 
+; CHECK: movs (M1, 1) [[ALIAS_SURF]](0,0)<1> [[SURFACE]](0)
 ; CHECK: mov (M1, 2) [[ALIAS_1]](0,0)<1> %tsc(0,0)<1;1,0>
 ; CHECK: mov (M1, 2) [[ALIAS_2]](0,0)<1> %tsc(0,0)<1;1,0>
 ; CHECK: mov (M1, 1) [[ALIAS_RES]](0,0)<1> [[TMC_1]](0,0)<0;1,0>
 ; CHECK: mov (M1, 1) [[ALIAS_RES]](0,1)<1> [[TMC_2]](0,0)<0;1,0>
-; CHECK: oword_st (2) [[SURFACE]] 0x0:ud [[RES]]
+; CHECK: lsc_store.ugm (M1, 1)  bti([[SURF]])[{{V[^ ]+}}]:a32  [[RES]]:d32x8t
 
 ; COM: ;;;;;;;;;; KERNEL ;;;;;;;;;;
 
diff --git a/IGC/VectorCompiler/test/GenXLegacyToLscTranslator/atomic.ll b/IGC/VectorCompiler/test/GenXLegacyToLscTranslator/atomic.ll
@@ -1,12 +1,12 @@
 ;=========================== begin_copyright_notice ============================
 ;
-; Copyright (C) 2023 Intel Corporation
+; Copyright (C) 2023-2024 Intel Corporation
 ;
 ; SPDX-License-Identifier: MIT
 ;
 ;============================ end_copyright_notice =============================
 
-; RUN: %opt %use_old_pass_manager% -enable-debugify -GenXLegacyToLscTranslator -march=genx64 -mcpu=XeHPC -mtriple=spir64-unknown-unknown -mattr=+translate_legacy_message -S < %s 2>&1 | FileCheck %s
+; RUN: %opt %use_old_pass_manager% -enable-debugify -GenXLegacyToLscTranslator -march=genx64 -mcpu=XeHPC -mtriple=spir64-unknown-unknown -S < %s 2>&1 | FileCheck %s
 
 target datalayout = "e-p:64:64-i64:64-n8:16:32:64"
 target triple = "genx64-unknown-unknown"
diff --git a/IGC/VectorCompiler/test/GenXLegacyToLscTranslator/gather-scatter.ll b/IGC/VectorCompiler/test/GenXLegacyToLscTranslator/gather-scatter.ll
@@ -1,12 +1,13 @@
 ;=========================== begin_copyright_notice ============================
 ;
-; Copyright (C) 2023 Intel Corporation
+; Copyright (C) 2023-2024 Intel Corporation
 ;
 ; SPDX-License-Identifier: MIT
 ;
 ;============================ end_copyright_notice =============================
 
-; RUN: %opt %use_old_pass_manager% -enable-debugify -GenXLegacyToLscTranslator -march=genx64 -mcpu=XeHPC -mtriple=spir64-unknown-unknown -mattr=+translate_legacy_message -S < %s 2>&1 | FileCheck %s
+; RUN: %opt %use_old_pass_manager% -enable-debugify -GenXLegacyToLscTranslator \
+; RUN: -march=genx64 -mcpu=XeHPC -mtriple=spir64-unknown-unknown -S < %s 2>&1 | FileCheck %s
 
 target datalayout = "e-p:64:64-i64:64-n8:16:32:64"
 target triple = "genx64-unknown-unknown"
diff --git a/IGC/VectorCompiler/test/GenXLegacyToLscTranslator/gather4-scatter4.ll b/IGC/VectorCompiler/test/GenXLegacyToLscTranslator/gather4-scatter4.ll
@@ -1,12 +1,13 @@
 ;=========================== begin_copyright_notice ============================
 ;
-; Copyright (C) 2023 Intel Corporation
+; Copyright (C) 2023-2024 Intel Corporation
 ;
 ; SPDX-License-Identifier: MIT
 ;
 ;============================ end_copyright_notice =============================
 
-; RUN: %opt %use_old_pass_manager% -enable-debugify -GenXLegacyToLscTranslator -march=genx64 -mcpu=XeHPC -mtriple=spir64-unknown-unknown -mattr=+translate_legacy_message -S < %s 2>&1 | FileCheck %s
+; RUN: %opt %use_old_pass_manager% -enable-debugify -GenXLegacyToLscTranslator \
+; RUN: -march=genx64 -mcpu=XeHPC -mtriple=spir64-unknown-unknown -S < %s 2>&1 | FileCheck %s
 
 target datalayout = "e-p:64:64-i64:64-n8:16:32:64"
 target triple = "genx64-unknown-unknown"
diff --git a/IGC/VectorCompiler/test/GenXLegacyToLscTranslator/media-block-ld.ll b/IGC/VectorCompiler/test/GenXLegacyToLscTranslator/media-block-ld.ll
@@ -10,8 +10,7 @@
 ; RUN: -mtriple=spir64-unknown-unknown  -S < %s | FileCheck %s
 
 ; RUN: %opt %use_old_pass_manager% -GenXLegacyToLscTranslator -march=genx64 -mcpu=XeHPG \
-; RUN: -mattr=+translate_legacy_message -mtriple=spir64-unknown-unknown  -S < %s | \
-; RUN: FileCheck --check-prefix=NOTYPED %s
+; RUN: -mtriple=spir64-unknown-unknown  -S < %s | FileCheck --check-prefix=NOTYPED %s
 
 ; COM: media.ld -> llvm.vc.internal.lsc.load.2d.tgm.bti
 
diff --git a/IGC/VectorCompiler/test/GenXLegacyToLscTranslator/media-block-st.ll b/IGC/VectorCompiler/test/GenXLegacyToLscTranslator/media-block-st.ll
@@ -7,12 +7,10 @@
 ;============================ end_copyright_notice =============================
 
 ; RUN: %opt %use_old_pass_manager% -GenXLegacyToLscTranslator -march=genx64 -mcpu=Xe2 \
-; RUN: -mattr=+translate_legacy_message -mtriple=spir64-unknown-unknown  -S < %s | \
-; RUN: FileCheck %s
+; RUN: -mtriple=spir64-unknown-unknown -S < %s | FileCheck %s
 
 ; RUN: %opt %use_old_pass_manager% -GenXLegacyToLscTranslator -march=genx64 -mcpu=XeHPG \
-; RUN: -mattr=+translate_legacy_message -mtriple=spir64-unknown-unknown  -S < %s | \
-; RUN: FileCheck --check-prefix=NOTYPED %s
+; RUN: -mtriple=spir64-unknown-unknown -S < %s | FileCheck --check-prefix=NOTYPED %s
 
 ; COM: media.st -> llvm.genx.lsc.store2d.typed.bti
 
diff --git a/IGC/VectorCompiler/test/GenXLegacyToLscTranslator/oword.ll b/IGC/VectorCompiler/test/GenXLegacyToLscTranslator/oword.ll
@@ -1,12 +1,13 @@
 ;=========================== begin_copyright_notice ============================
 ;
-; Copyright (C) 2023 Intel Corporation
+; Copyright (C) 2023-2024 Intel Corporation
 ;
 ; SPDX-License-Identifier: MIT
 ;
 ;============================ end_copyright_notice =============================
 
-; RUN: %opt %use_old_pass_manager% -enable-debugify -GenXLegacyToLscTranslator -march=genx64 -mcpu=XeHPC -mtriple=spir64-unknown-unknown -mattr=+translate_legacy_message -S < %s 2>&1 | FileCheck %s
+; RUN: %opt %use_old_pass_manager% -enable-debugify -GenXLegacyToLscTranslator \
+; RUN: -march=genx64 -mcpu=XeHPC -mtriple=spir64-unknown-unknown -S < %s 2>&1 | FileCheck %s
 
 target datalayout = "e-p:64:64-i64:64-n8:16:32:64"
 target triple = "genx64-unknown-unknown"

Original file line number	Diff line number	Diff line change
`@@ -1,6 +1,6 @@`
`1`	`1`	`;=========================== begin_copyright_notice ============================`
`2`	`2`	`;`
`3`		`-; Copyright (C) 2023 Intel Corporation`
	`3`	`+; Copyright (C) 2023-2024 Intel Corporation`
`4`	`4`	`;`
`5`	`5`	`; SPDX-License-Identifier: MIT`
`6`	`6`	`;`
`@@ -14,6 +14,7 @@`
`14`	`14`
`15`	`15`	`; COM: ;;;;;;;;;; CHECKERS ;;;;;;;;;;`
`16`	`16`
	`17`	`+; CHECK: .decl {{V[^ ]+}} v_type=G type=hf num_elts=8`
`17`	`18`	`; CHECK: .decl [[SRC:V[^ ]+]] v_type=G type=hf num_elts=8`
`18`	`19`	`; CHECK: cos (M1, 8) [[COS:V[^ ]+]](0,0)<1> [[SRC]](0,0)<1;1,0>`
`19`	`20`	`; CHECK: exp (M1, 8) [[EXP:V[^ ]+]](0,0)<1> [[SRC]](0,0)<1;1,0>`
Original file line number	Diff line number	Diff line change
`@@ -1,12 +1,12 @@`
`1`	`1`	`;=========================== begin_copyright_notice ============================`
`2`	`2`	`;`
`3`		`-; Copyright (C) 2023 Intel Corporation`
	`3`	`+; Copyright (C) 2023-2024 Intel Corporation`
`4`	`4`	`;`
`5`	`5`	`; SPDX-License-Identifier: MIT`
`6`	`6`	`;`
`7`	`7`	`;============================ end_copyright_notice =============================`
`8`	`8`
`9`		`-; RUN: %opt %use_old_pass_manager% -enable-debugify -GenXLegacyToLscTranslator -march=genx64 -mcpu=XeHPC -mtriple=spir64-unknown-unknown -mattr=+translate_legacy_message -S < %s 2>&1 \| FileCheck %s`
	`9`	`+; RUN: %opt %use_old_pass_manager% -enable-debugify -GenXLegacyToLscTranslator -march=genx64 -mcpu=XeHPC -mtriple=spir64-unknown-unknown -S < %s 2>&1 \| FileCheck %s`
`10`	`10`
`11`	`11`	`target datalayout = "e-p:64:64-i64:64-n8:16:32:64"`
`12`	`12`	`target triple = "genx64-unknown-unknown"`
Original file line number	Diff line number	Diff line change
`@@ -1,12 +1,13 @@`
`1`	`1`	`;=========================== begin_copyright_notice ============================`
`2`	`2`	`;`
`3`		`-; Copyright (C) 2023 Intel Corporation`
	`3`	`+; Copyright (C) 2023-2024 Intel Corporation`
`4`	`4`	`;`
`5`	`5`	`; SPDX-License-Identifier: MIT`
`6`	`6`	`;`
`7`	`7`	`;============================ end_copyright_notice =============================`
`8`	`8`
`9`		`-; RUN: %opt %use_old_pass_manager% -enable-debugify -GenXLegacyToLscTranslator -march=genx64 -mcpu=XeHPC -mtriple=spir64-unknown-unknown -mattr=+translate_legacy_message -S < %s 2>&1 \| FileCheck %s`
	`9`	`+; RUN: %opt %use_old_pass_manager% -enable-debugify -GenXLegacyToLscTranslator \`
	`10`	`+; RUN: -march=genx64 -mcpu=XeHPC -mtriple=spir64-unknown-unknown -S < %s 2>&1 \| FileCheck %s`
`10`	`11`
`11`	`12`	`target datalayout = "e-p:64:64-i64:64-n8:16:32:64"`
`12`	`13`	`target triple = "genx64-unknown-unknown"`