Use V_MASK in dynamic extract element instructions in a subspan chain

This change is to use V_MASK as a predicate for indirect move instruction.

Author: krystian-andrzejewski

IGC/Compiler/CISACodeGen/EmitVISAPass.cpp

@@ -4713,11 +4713,11 @@ CVariable* EmitPass::GetCombinedVMaskPred(CVariable* basePredicate)
         return basePredicate;
 
     bool subspan = m_encoder->IsSubSpanDestination();
-    if ((IGC_IS_FLAG_ENABLED(UseVMaskPredicate) || IGC_IS_FLAG_ENABLED(UseVMaskPredicateForLoads)) &&
+    if ((IGC_IS_FLAG_ENABLED(UseVMaskPredicate) || IGC_IS_FLAG_ENABLED(UseVMaskPredicateForLoads) || IGC_IS_FLAG_ENABLED(UseVMaskPredicateForIndirectMove)) &&
         subspan && !m_destination->IsUniform())
     {
         CVariable* vmaskPredicate = m_vMaskPredForSubplane;
-        if (IGC_IS_FLAG_ENABLED(UseVMaskPredicateForLoads))
+        if (IGC_IS_FLAG_ENABLED(UseVMaskPredicateForLoads) || IGC_IS_FLAG_ENABLED(UseVMaskPredicateForIndirectMove))
         {
             vmaskPredicate = m_currShader->GetNewVariable(
                 numLanes(m_SimdMode),
@@ -9995,9 +9995,15 @@ void EmitPass::emitExtract(llvm::Instruction* inst)
                 m_encoder->Push();
 
                 dstAlias[i] = m_currShader->GetNewAlias(m_destination, m_destination->GetType(), (dstNElts / 2) * vecTypeSize * i, dstNElts / 2);
+                CVariable* predicate = IGC_IS_FLAG_ENABLED(UseVMaskPredicateForIndirectMove) ? GetCombinedVMaskPred() : nullptr;
+
                 // finally, we move the indirectly addressed values to the destination register
                 m_encoder->SetMask(i == 0 ? EMASK_H1 : EMASK_H2);
                 m_encoder->SetSimdSize(SIMDMode::SIMD16);
+
+                // to avoid out-of-bounds indirect access (exceeding the maximum number of GRFs)
+                m_encoder->SetPredicate(predicate);
+
                 m_encoder->Copy(dstAlias[i], pDstArrElm);
                 m_encoder->Push();
             }
@@ -10016,6 +10022,9 @@ void EmitPass::emitExtract(llvm::Instruction* inst)
             m_encoder->AddrAdd(pDstArrElm, vector, pOffset3);
             m_encoder->Push();
 
+            // to avoid out-of-bounds indirect access (exceeding the maximum number of GRFs)
+            m_encoder->SetPredicate(IGC_IS_FLAG_ENABLED(UseVMaskPredicateForIndirectMove) ? GetCombinedVMaskPred() : nullptr);
+
             // finally, we move the indirectly addressed values to the destination register
             m_encoder->Copy(m_destination, pDstArrElm);
             m_encoder->Push();
@@ -18118,7 +18127,7 @@ void EmitPass::emitLSCVectorLoad_subDW(LSC_CACHE_OPTS CacheOpts, bool UseA32,
         if (doUniformLoad)
             m_encoder->SetNoMask();
         else
-            m_encoder->SetPredicate(GetCombinedVMaskPred(flag));
+            m_encoder->SetPredicate(IGC_IS_FLAG_ENABLED(UseVMaskPredicateForLoads) ? GetCombinedVMaskPred(flag) : flag);
 
         emitLSCLoad(CacheOpts, gatherDst,
                     eOffset, EltBytes * 8, 1, 0, &Resource, AddrSize,
@@ -18361,7 +18370,7 @@ void EmitPass::emitLSCVectorLoad(Instruction* inst,
                     dVisaTy, (uint16_t)eltOffBytes, (uint16_t)nbelts);
             }
 
-            m_encoder->SetPredicate(GetCombinedVMaskPred(flag));
+            m_encoder->SetPredicate(IGC_IS_FLAG_ENABLED(UseVMaskPredicateForLoads) ? GetCombinedVMaskPred(flag) : flag);
 
             VectorMessage::MESSAGE_KIND messageType = VecMessInfo.insts[i].kind;
             IGC_ASSERT_MESSAGE(

IGC/Compiler/CISACodeGen/EmitVISAPass.hpp

@@ -375,7 +375,7 @@ class EmitPass : public llvm::FunctionPass
     CVariable* GetVMaskPred(CVariable*& predicate);
     void createVMaskPred(CVariable*& predicate);
     void UseVMaskPred();
-    CVariable* GetCombinedVMaskPred(CVariable* basePredicate);
+    CVariable* GetCombinedVMaskPred(CVariable* basePredicate = nullptr);
     CVariable* m_vMaskPredForSubplane = nullptr;
 
     void emitGradientX(const SSource& source, const DstModifier& modifier);

IGC/common/igc_flags.h

@@ -424,7 +424,8 @@ DECLARE_IGC_REGKEY(bool, NoCatchAllDebugLine,           false, "Don't emit speci
 DECLARE_IGC_REGKEY(bool, EnableTestSplitI64,            false, "Test legalization that split i64 store unnecessarily, to be deleted once test is done[temp]", true)
 DECLARE_IGC_REGKEY(bool, ShaderDumpTranslationOnly,     false, "Dump LLVM IR right after translation from SPIRV to stderr and ignore all passes", false)
 DECLARE_IGC_REGKEY(bool, UseVMaskPredicate,             false, "Use VMask as predicate for subspan usage", false)
-DECLARE_IGC_REGKEY(bool, UseVMaskPredicateForLoads,     true,  "Use VMask as predicate for subspan usage (loads only)", true)
+DECLARE_IGC_REGKEY(bool, UseVMaskPredicateForLoads, true, "Use VMask as predicate for subspan usage (loads only)", true)
+DECLARE_IGC_REGKEY(bool, UseVMaskPredicateForIndirectMove, true, "Use VMask as predicate for subspan usage (indirect mov only)", true)
 DECLARE_IGC_REGKEY(bool, StackOverflowDetection,        false, "Inserts checks for stack overflow when stack calls are used.", true)
 
 DECLARE_IGC_GROUP("IGC Features")