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DianaChenigcbot
DianaChen
authored and
igcbot
committed
vISA: support platforms ARL and XE2
Add platforms Xe_ARL and Xe2 to vISA::TARGET_PLATFORM
1 parent 2c2a649 commit 2998e86

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43 files changed

+1601
-58
lines changed

‎inc/common/sku_wa_defs.h

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -626,3 +626,9 @@ SPDX-License-Identifier: MIT
626626
"Workaround",
627627
WA_BUG_TYPE_UNKNOWN,
628628
WA_BUG_PERF_IMPACT_UNKNOWN, WA_COMPONENT_UNKNOWN)
629+
630+
WA_DECLARE(
631+
Wa_22017182272,
632+
"Workaround",
633+
WA_BUG_TYPE_UNKNOWN,
634+
WA_BUG_PERF_IMPACT_UNKNOWN, WA_COMPONENT_UNKNOWN)

‎visa/BinaryEncodingIGA.cpp

Lines changed: 13 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -361,12 +361,16 @@ BinaryEncodingIGA::getIGAInternalPlatform(TARGET_PLATFORM genxPlatform) {
361361
break;
362362
case Xe_DG2:
363363
case Xe_MTL:
364+
case Xe_ARL:
364365
platform = Platform::XE_HPG;
365366
break;
366367
case Xe_PVC:
367368
case Xe_PVCXT:
368369
platform = Platform::XE_HPC;
369370
break;
371+
case Xe2:
372+
platform = Platform::XE2;
373+
break;
370374
default:
371375
break;
372376
}
@@ -1679,8 +1683,17 @@ SendDesc BinaryEncodingIGA::encodeExDescRegA0(G4_INST *sendInst,
16791683
const bool isLscBti = isLsc && descG4->getLscAddrType() == LSC_ADDR_TYPE_BTI;
16801684
const bool isUgm = sendInst->getMsgDesc()->getSFID() == vISA::SFID::UGM;
16811685
encodeExBso &= !isLscBti;
1686+
encodeExBso &= (platform < Xe2 || !isUgm);
16821687
if (encodeExBso)
16831688
sdos.extraOpts.add(InstOpt::EXBSO);
1689+
if (isLsc && isUgm && !encodeExBso) {
1690+
bool isLscBssOrSs = descG4->getLscAddrType() == LSC_ADDR_TYPE_BSS ||
1691+
descG4->getLscAddrType() == LSC_ADDR_TYPE_SS;
1692+
if (isLscBssOrSs && descG4->getBti() != nullptr) {
1693+
// BSS/SS with a0 reg (ExDesc.IsReg) with UGM
1694+
sdos.exDescImmOff = descG4->getExDescImmOff();
1695+
}
1696+
}
16841697

16851698
// G4 IR keeps Src1.Length (xlen) separate. So it's known,
16861699
// (even with a reg desc in nonExBSO mode)

‎visa/BuildIR.h

Lines changed: 27 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -2096,8 +2096,16 @@ class IR_Builder {
20962096
G4_SrcRegRegion *lscLoadEffectiveAddress(
20972097
LSC_OP lscOp, LSC_SFID lscSfid, G4_Predicate *pred, G4_ExecSize execSize,
20982098
VISA_EMask_Ctrl execCtrl, LSC_ADDR addrInfo, int bytesPerDataElem,
2099-
const G4_Operand *surface, G4_SrcRegRegion *addr, uint32_t &exDesc
2100-
);
2099+
const G4_Operand *surface, G4_SrcRegRegion *addr, uint32_t &exDesc,
2100+
uint32_t &exDescImmOff);
2101+
2102+
// try and promote an immediate offset to LSC descriptor
2103+
// (doesn't work for block2d)
2104+
bool lscTryPromoteImmOffToExDesc(LSC_OP lscOp, LSC_SFID lscSfid,
2105+
LSC_ADDR addrInfo, int bytesPerDataElem,
2106+
const G4_Operand *surface,
2107+
uint32_t &exDescImm, uint32_t &exDescImmOff);
2108+
21012109
G4_SrcRegRegion *lscCheckRegion(G4_Predicate *pred, G4_ExecSize execSize,
21022110
VISA_EMask_Ctrl execCtrl,
21032111
G4_SrcRegRegion *src);
@@ -2331,6 +2339,23 @@ class IR_Builder {
23312339
bool isNativeSIMDSize, bool isFP16Return,
23322340
bool isFP16Input) const;
23332341
};
2342+
2343+
constexpr VISALscImmOffOpts getLscImmOffOpt(LSC_ADDR_TYPE addrType) {
2344+
switch (addrType) {
2345+
case LSC_ADDR_TYPE_FLAT:
2346+
return VISA_LSC_IMMOFF_ADDR_TYPE_FLAT;
2347+
case LSC_ADDR_TYPE_BSS:
2348+
return VISA_LSC_IMMOFF_ADDR_TYPE_BSS;
2349+
case LSC_ADDR_TYPE_SS:
2350+
return VISA_LSC_IMMOFF_ADDR_TYPE_SS;
2351+
case LSC_ADDR_TYPE_BTI:
2352+
case LSC_ADDR_TYPE_ARG:
2353+
return VISA_LSC_IMMOFF_ADDR_TYPE_BTI;
2354+
default:
2355+
break;
2356+
}
2357+
return VISA_LSC_IMMOFF_INVALID;
2358+
}
23342359
} // namespace vISA
23352360

23362361
// G4IR instructions added by JIT that do not result from lowering

‎visa/BuildIRImpl.cpp

Lines changed: 16 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2518,6 +2518,12 @@ G4_SendDescRaw *IR_Builder::createLscMsgDesc(
25182518
}
25192519
}
25202520

2521+
uint32_t exDescImmOff = 0;
2522+
if (lscTryPromoteImmOffToExDesc(op, lscSfid, addr, dataSizeBits / 8, surface,
2523+
exDesc, exDescImmOff)) {
2524+
addr.immOffset = 0;
2525+
}
2526+
25212527
vISA_ASSERT(addr.immOffset == 0, "invalid address immediate offset");
25222528

25232529
SFID sfid = LSC_SFID_To_SFID(lscSfid);
@@ -2566,6 +2572,9 @@ G4_SendDescRaw *IR_Builder::createLscMsgDesc(
25662572

25672573
G4_SendDescRaw *g4desc =
25682574
createSendMsgDesc(sfid, desc, exDesc, src1Len, access, surface);
2575+
if (exDescImmOff) {
2576+
g4desc->setExDescImmOff(exDescImmOff);
2577+
}
25692578
g4desc->setLdStAttr(otherAttrs);
25702579
return g4desc;
25712580
}
@@ -3279,6 +3288,8 @@ void IR_Builder::doSimplification(G4_INST *inst) {
32793288
// - indices to src are all within src.
32803289
// - destination stride in bytes must be equal to the source element size in
32813290
// bytes.
3291+
3292+
// - both src and dst are dword data type:
32823293
bool canConvertMovToMovi =
32833294
inst->opcode() == G4_mov && inst->getExecSize() == g4::SIMD8 &&
32843295
inst->isRawMov() && inst->getDst() &&
@@ -3290,6 +3301,11 @@ void IR_Builder::doSimplification(G4_INST *inst) {
32903301
inst->getSrc(0)->getTypeSize() ==
32913302
inst->getDst()->getTypeSize() *
32923303
inst->getDst()->asDstRegRegion()->getHorzStride();
3304+
if (getPlatform() >= Xe2) {
3305+
canConvertMovToMovi = canConvertMovToMovi &&
3306+
IS_DTYPE(inst->getDst()->getType()) &&
3307+
IS_DTYPE(inst->getSrc(0)->getType());
3308+
}
32933309
if (canConvertMovToMovi) {
32943310
// Convert 'mov' to 'movi' if the following conditions are met.
32953311

‎visa/CISA.l

Lines changed: 35 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -466,6 +466,13 @@ lsc_atomic_iinc|lsc_atomic_idec|lsc_atomic_iadd|lsc_atomic_load|lsc_atomic_store
466466
return LSC_ATOMIC_MNEMONIC;
467467
}
468468

469+
lsc_apndctr_atomic_add|lsc_apndctr_atomic_sub|lsc_apndctr_atomic_store {
470+
TRACE("** lsc_apndctr_atomic INST");
471+
CISAlval.lsc_subOpcode = str2lscop(yytext);
472+
// this is set in the parser based on the SFID
473+
// CISAlval.lsc_opcode = ISA_LSC_UNTYPED;
474+
return LSC_ATOMIC_MNEMONIC;
475+
}
469476

470477
lsc_read_state_info {
471478
TRACE("** lsc_read_state_info INST");
@@ -733,15 +740,30 @@ sample_3d|sample_b|sample_l|sample_c|sample_d|sample_b_c|sample_l_c|sample_d_c|s
733740
return SAMPLE_3D_OP;
734741
}
735742

743+
sample_po|sample_po_b|sample_po_l|sample_po_c|sample_po_d|sample_po_l_c|sample_po_lz|sample_po_c_lz {
744+
TRACE("** SAMPLE_3D");
745+
CISAlval.sample3DOp = str2SampleOpcode(yytext, pBuilder->getPlatform());
746+
return SAMPLE_3D_OP;
747+
}
736748

737-
749+
sample_mlod|sample_c_mlod|sample_d_c_mlod {
750+
TRACE("** SAMPLE_3D");
751+
CISAlval.sample3DOp = str2SampleOpcode(yytext, pBuilder->getPlatform());
752+
return SAMPLE_3D_OP;
753+
}
738754

739755
load_3d|load_mcs|load_2dms_w|load_lz {
740756
TRACE("** LOAD_3D");
741757
CISAlval.sample3DOp = str2SampleOpcode(yytext, pBuilder->getPlatform());
742758
return LOAD_3D_OP;
743759
}
744760

761+
load_l {
762+
TRACE("** LOAD_3D");
763+
CISAlval.sample3DOp = str2SampleOpcode(yytext, pBuilder->getPlatform());
764+
return LOAD_3D_OP;
765+
}
766+
745767
sample4|sample4_c {
746768
TRACE("** SAMPLE4_3D");
747769
CISAlval.sample3DOp = str2SampleOpcode(yytext, pBuilder->getPlatform());
@@ -754,7 +776,17 @@ sample4_po|sample4_po_c {
754776
return SAMPLE4_3D_OP;
755777
}
756778

779+
sample4_po_b|sample4_po_l|sample4_po_l_c|sample4_po_i|sample4_po_i_c {
780+
TRACE("** SAMPLE4_3D");
781+
CISAlval.sample3DOp = str2SampleOpcode(yytext, pBuilder->getPlatform());
782+
return SAMPLE4_3D_OP;
783+
}
757784

785+
sample4_i|sample4_l|sample4_b|sample4_i_c|sample4_l_c {
786+
TRACE("** SAMPLE4_3D");
787+
CISAlval.sample3DOp = str2SampleOpcode(yytext, pBuilder->getPlatform());
788+
return SAMPLE4_3D_OP;
789+
}
758790

759791
resinfo {
760792
TRACE("** RESINFO_3D");
@@ -1078,6 +1110,8 @@ type[ ]*=[ ]*(ud|d|uw|w|ub|b|df|f|bool|uq|q|UD|D|UW|W|UB|B|DF|F|Bool|BOOL|UQ|Q|h
10781110
CISAlval.lsc_caching_opt = LSC_CACHING_WRITETHROUGH;
10791111
} else if (strcmp(yytext+1,"st") == 0) {
10801112
CISAlval.lsc_caching_opt = LSC_CACHING_STREAMING;
1113+
} else if (strcmp(yytext+1,"cc") == 0) {
1114+
CISAlval.lsc_caching_opt = LSC_CACHING_CONSTCACHED;
10811115
} else { /* ri */
10821116
CISAlval.lsc_caching_opt = LSC_CACHING_READINVALIDATE;
10831117
}

‎visa/CISA.y

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -250,6 +250,11 @@ std::vector<attr_gen_struct*> AttrOptVar;
250250
VISA_opnd *surface; // can be imm or reg
251251
int surfaceIndex;
252252
} lsc_addr_model;
253+
struct {
254+
VISA_opnd *reg;
255+
LSC_DATA_SHAPE_TYPED_BLOCK2D shape_typed2d;
256+
} lsc_data_operand_typed2d;
257+
LSC_DATA_SHAPE_TYPED_BLOCK2D lsc_data_shape_typed2d;
253258

254259
// Align Support in Declaration
255260
VISA_Align align;

‎visa/Common_ISA.cpp

Lines changed: 56 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -69,24 +69,80 @@ static const char *getSampleOp3DNameOrNull(VISASampler3DSubOpCode opcode,
6969
return "sampleinfo";
7070
case VISA_3D_SAMPLE_KILLPIX: // 0xC
7171
return "sample+killpix";
72+
case VISA_3D_GATHER4_L: // 0xD
73+
return "sample4_l";
74+
case VISA_3D_GATHER4_B: // 0xE
75+
return "sample4_b";
76+
case VISA_3D_GATHER4_I: // 0xF
77+
return "sample4_i";
7278
case VISA_3D_GATHER4_C: // 0x10
7379
return "sample4_c";
7480
case VISA_3D_GATHER4_PO: // 0x11
81+
// Xe2 reuses GATHER4_PO* opcode values, Xe2 doesn't
82+
// have GATHER4_PO*.
83+
vISA_ASSERT(VISA_3D_SAMPLE_D_C_MLOD == VISA_3D_GATHER4_PO,
84+
"Code below needs update");
85+
if (platform >= Xe2) {
86+
return "sample_d_c_mlod";
87+
}
7588
return "sample4_po";
7689
case VISA_3D_GATHER4_PO_C: // 0x12
90+
vISA_ASSERT(VISA_3D_SAMPLE_MLOD == VISA_3D_GATHER4_PO_C,
91+
"Code below needs update");
92+
if (platform >= Xe2) {
93+
return "sample_mlod";
94+
}
7795
return "sample4_po_c";
96+
case VISA_3D_SAMPLE_C_MLOD: // 0x13
97+
return "sample_c_mlod";
7898
case VISA_3D_SAMPLE_D_C: // 0x14
7999
return "sample_d_c";
100+
case VISA_3D_GATHER4_I_C: // 0x15
101+
return "sample4_i_c";
102+
case VISA_3D_GATHER4_L_C: // 0x17
103+
return "sample4_l_c";
80104
case VISA_3D_SAMPLE_LZ: // 0x18
81105
return "sample_lz";
82106
case VISA_3D_SAMPLE_C_LZ: // 0x19
83107
return "sample_c_lz";
84108
case VISA_3D_LD_LZ: // 0x1A
85109
return "load_lz";
110+
case VISA_3D_LD_L: // 0x1B
111+
return "load_l";
86112
case VISA_3D_LD2DMS_W: // 0x1C
87113
return "load_2dms_w";
88114
case VISA_3D_LD_MCS: // 0x1D
89115
return "load_mcs";
116+
case VISA_3D_SAMPLE_PO:
117+
return "sample_po";
118+
case VISA_3D_SAMPLE_PO_B:
119+
return "sample_po_b";
120+
case VISA_3D_SAMPLE_PO_L:
121+
return "sample_po_l";
122+
case VISA_3D_SAMPLE_PO_C:
123+
return "sample_po_c";
124+
case VISA_3D_SAMPLE_PO_D:
125+
return "sample_po_d";
126+
case VISA_3D_SAMPLE_PO_L_C:
127+
return "sample_po_l_c";
128+
case VISA_3D_GATHER4_PO_PACKED:
129+
return "sample4_po";
130+
case VISA_3D_GATHER4_PO_PACKED_L:
131+
return "sample4_po_l";
132+
case VISA_3D_GATHER4_PO_PACKED_B:
133+
return "sample4_po_b";
134+
case VISA_3D_GATHER4_PO_PACKED_I:
135+
return "sample4_po_i";
136+
case VISA_3D_GATHER4_PO_PACKED_C:
137+
return "sample4_po_c";
138+
case VISA_3D_GATHER4_PO_PACKED_I_C:
139+
return "sample4_po_i_c";
140+
case VISA_3D_GATHER4_PO_PACKED_L_C:
141+
return "sample4_po_l_c";
142+
case VISA_3D_SAMPLE_PO_LZ:
143+
return "sample_po_lz";
144+
case VISA_3D_SAMPLE_PO_C_LZ:
145+
return "sample_po_c_lz";
90146
default:
91147
return nullptr;
92148
}

‎visa/Common_ISA_util.cpp

Lines changed: 26 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1393,6 +1393,17 @@ const raw_opnd &getRawOperand(const CISA_INST *inst, unsigned i) {
13931393
return inst->opnd_array[i]->_opnd.r_opnd;
13941394
}
13951395

1396+
bool isNullRawOperand(const CISA_INST *inst, unsigned i) {
1397+
vISA_ASSERT(inst, "Argument Exception: argument inst is NULL.");
1398+
vISA_ASSERT(inst->opnd_num > i,
1399+
"No such operand, i, for instruction inst.");
1400+
return inst->opnd_array[i]->_opnd.r_opnd.index == 0;
1401+
}
1402+
1403+
bool isNotNullRawOperand(const CISA_INST *inst, unsigned i) {
1404+
return !isNullRawOperand(inst, i);
1405+
}
1406+
13961407
const vector_opnd &getVectorOperand(const CISA_INST *inst, unsigned i) {
13971408
vISA_ASSERT(inst, "Argument Exception: argument inst is NULL.");
13981409
vISA_ASSERT(inst->opnd_num > i,
@@ -1595,6 +1606,21 @@ LSC_CACHE_OPTS convertLSCLoadStoreCacheControlEnum(LSC_L1_L3_CC L1L3cc,
15951606
else
15961607
cacheOpts = {LSC_CACHING_WRITEBACK, LSC_CACHING_WRITEBACK};
15971608
break;
1609+
case LSC_L1UC_L3CC:
1610+
if (isLoad) {
1611+
cacheOpts = {LSC_CACHING_UNCACHED, LSC_CACHING_CONSTCACHED};
1612+
break;
1613+
}
1614+
case LSC_L1C_L3CC:
1615+
if (isLoad) {
1616+
cacheOpts = {LSC_CACHING_CACHED, LSC_CACHING_CONSTCACHED};
1617+
break;
1618+
}
1619+
case LSC_L1IAR_L3IAR:
1620+
if (isLoad) {
1621+
cacheOpts = {LSC_CACHING_READINVALIDATE, LSC_CACHING_READINVALIDATE};
1622+
break;
1623+
}
15981624
default:
15991625
vISA_ASSERT_UNREACHABLE("unsupported caching option");
16001626
break;

‎visa/Common_ISA_util.h

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -111,6 +111,9 @@ template <typename T> T getPrimitiveOperand(const CISA_INST *inst, unsigned i) {
111111

112112
const raw_opnd &getRawOperand(const CISA_INST *inst, unsigned i);
113113

114+
bool isNullRawOperand(const CISA_INST *inst, unsigned i);
115+
bool isNotNullRawOperand(const CISA_INST *inst, unsigned i);
116+
114117
const vector_opnd &getVectorOperand(const CISA_INST *inst, unsigned i);
115118

116119
CISA_opnd_type getOperandType(const CISA_INST *inst, unsigned i);

‎visa/G4_BB.cpp

Lines changed: 18 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -588,6 +588,10 @@ int G4_BB::getConflictTimesForTGL(std::ostream &output, int *firstRegCandidate,
588588

589589
if (reducedBundles) {
590590
bundleID = (firstRegCandidate[i] % 16) / 2;
591+
}
592+
if (parent->builder->has64bundleSize2GRFPerBank()) {
593+
bankID = (firstRegCandidate[i] % 4) / 2;
594+
bundleID = (firstRegCandidate[i] % 32) / 4;
591595
}
592596
// Same bank and same bundle
593597
if (bundles[bankID][bundleID] != -1) {
@@ -895,13 +899,27 @@ static bool hasInternalConflict(IR_Builder *builder, int reg1, int reg2) {
895899
bankID2 = (reg2 % 4) / 2;
896900
}
897901

902+
if (builder->has64bundleSize2GRFPerBank()) {
903+
bundleID1 = (reg1 % 32) / 4;
904+
bankID1 = (reg1 % 4) / 2;
905+
bundleID2 = (reg2 % 32) / 4;
906+
bankID2 = (reg2 % 4) / 2;
907+
}
908+
898909
if (builder->hasOneGRFBank16Bundles()) {
899910
bundleID1 = (reg1 % 64) / 4;
900911
bankID1 = reg1 % 2;
901912
bundleID2 = (reg2 % 64) / 4;
902913
bankID2 = reg2 % 2;
903914
}
904915

916+
if (builder->has64bundleSize()) {
917+
bundleID1 = (reg1 % 16) / 2;
918+
bankID1 = reg1 % 2;
919+
bundleID2 = (reg2 % 16) / 2;
920+
bankID2 = reg2 % 2;
921+
}
922+
905923
return ((bankID1 == bankID2) && (bundleID1 == bundleID2));
906924
}
907925

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