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aparshin-intel
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moved Region class to generic Utils
CMRegion and Region classes are actually the same thing. It's just that Region class does not need Instruction interface and it is a primary method to construct regions from a *Value*
1 parent f008d20 commit 29b536e

38 files changed

+363
-324
lines changed

‎IGC/VectorCompiler/include/vc/Utils/GenX/Region.h

Lines changed: 17 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -220,6 +220,23 @@ class CMRegion {
220220
Value *getStartIdx(const Twine &Name, Instruction *InsertBefore, const DebugLoc &DL);
221221
};
222222

223+
/* Note: Region is a more specialized class for constructing Regions,
224+
the primary difference is that Region class requires only Value interface
225+
and is not aware about Instruction stuff.
226+
*/
227+
class Region : public CMRegion {
228+
public:
229+
// Default constructor: assume single element
230+
Region() : CMRegion() {}
231+
// Construct from a type.
232+
Region(Type *Ty, const DataLayout *DL = nullptr) : CMRegion(Ty, DL) {};
233+
// Construct from a value.
234+
Region(Value *V, const DataLayout *DL = nullptr) : CMRegion(V, DL) {};
235+
// Construct from a bitmap of which elements to set (legal 1D region)
236+
Region(unsigned Bits, unsigned ElementBytes)
237+
: CMRegion(Bits, ElementBytes) {};
238+
};
239+
223240
inline raw_ostream &operator<<(raw_ostream &OS, const CMRegion &R) {
224241
R.print(OS);
225242
return OS;

‎IGC/VectorCompiler/lib/GenXCodeGen/CMakeLists.txt

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -68,7 +68,7 @@ set(CODEGEN_SOURCES
6868
GenXRawSendRipper.cpp
6969
GenXReduceIntSize.cpp
7070
GenXInstCombineCleanup.cpp
71-
GenXRegion.cpp
71+
GenXRegionUtils.cpp
7272
GenXRegionCollapsing.cpp
7373
GenXRematerialization.cpp
7474
GenXSimdCFConformance.cpp

‎IGC/VectorCompiler/lib/GenXCodeGen/GenXAddressCommoning.cpp

Lines changed: 8 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -77,7 +77,6 @@ SPDX-License-Identifier: MIT
7777
#include "GenXLiveness.h"
7878
#include "GenXModule.h"
7979
#include "GenXNumbering.h"
80-
#include "GenXRegion.h"
8180
#include "GenXUtil.h"
8281
#include "vc/GenXOpts/Utils/RegCategory.h"
8382
#include "llvm-c/Core.h"
@@ -772,7 +771,7 @@ bool GenXAddressCommoning::tryConvertWholeRegion(SmallVector<Extract, 4> &Extrac
772771
// check every extract
773772
for (unsigned Idx = 0, End = Extracts.size(); Idx < End; ++Idx) {
774773
Instruction *RdR = cast<Instruction>(Extracts[Idx].Addr->getOperand(0));
775-
Region R(RdR, BaleInfo());
774+
Region R = makeRegionFromBaleInfo(RdR, BaleInfo());
776775
if (R.NumElements > 1 && R.Stride > 1)
777776
return false;
778777
// all address-conv must be in the same basic block
@@ -808,7 +807,7 @@ bool GenXAddressCommoning::tryConvertWholeRegion(SmallVector<Extract, 4> &Extrac
808807
for (unsigned Idx2 = 0, End2 = Extracts.size(); Idx2 < End2; ++Idx2) {
809808
auto OldConv = Extracts[Idx2].Addr;
810809
Instruction *OldExtract = cast<Instruction>(OldConv->getOperand(0));
811-
Region R2(OldExtract, BaleInfo());
810+
Region R2 = makeRegionFromBaleInfo(OldExtract, BaleInfo());
812811
while (!OldConv->use_empty()) {
813812
auto ui = OldConv->use_begin();
814813
auto user = cast<Instruction>(ui->getUser());
@@ -862,7 +861,8 @@ bool GenXAddressCommoning::vectorizeAddrsFromOneVector(
862861
Instruction *Addr = *i;
863862
LLVM_DEBUG(Addr->dump());
864863

865-
Region R(cast<Instruction>(Addr->getOperand(0)), BaleInfo());
864+
Region R = makeRegionFromBaleInfo(cast<Instruction>(Addr->getOperand(0)),
865+
BaleInfo());
866866
LLVM_DEBUG(dbgs() << " [" << R.Offset << "]\n");
867867

868868
Extracts.push_back(Extract(Addr, R.Offset));
@@ -936,14 +936,16 @@ bool GenXAddressCommoning::vectorizeAddrsFromOneVector(
936936
LLVM_DEBUG(dbgs() << "Sequence of " << Num << " instructions found. First one is:\n");
937937
LLVM_DEBUG(FirstRdR->dump());
938938
LLVM_DEBUG(dbgs() << "\n");
939-
Region R(FirstRdR, BaleInfo());
939+
Region R = makeRegionFromBaleInfo(FirstRdR, BaleInfo());
940940
R.NumElements = R.Width = Num;
941941
R.Stride = Diff / R.ElementBytes;
942942
// See how big we can legally make the region.
943943
unsigned InputNumElements =
944944
cast<IGCLLVM::FixedVectorType>(FirstRdR->getOperand(0)->getType())
945945
->getNumElements();
946-
Num = R.getLegalSize(0, /*Allow2D=*/true, InputNumElements, ST);
946+
IGC_ASSERT(ST);
947+
Num = getLegalRegionSizeForTarget(*ST, R, 0, true /*Allow2D*/,
948+
InputNumElements);
947949
if (Num == 1)
948950
continue;
949951
// Even after legalizing the region, we can still vectorize to more than

‎IGC/VectorCompiler/lib/GenXCodeGen/GenXAlignmentInfo.cpp

Lines changed: 7 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -22,19 +22,22 @@ SPDX-License-Identifier: MIT
2222

2323
#include "IGC/common/StringMacros.hpp"
2424

25-
#include <algorithm>
2625
#include "GenX.h"
2726
#include "GenXAlignmentInfo.h"
27+
#include "GenXRegionUtils.h"
2828
#include "GenXBaling.h"
29-
#include "GenXRegion.h"
29+
3030
#include "llvm/IR/Constants.h"
3131
#include "llvm/IR/Function.h"
3232
#include "llvm/IR/Instructions.h"
3333
#include "llvm/IR/Intrinsics.h"
3434
#include "llvm/Support/Debug.h"
35-
#include <set>
35+
3636
#include "Probe/Assertion.h"
3737

38+
#include <algorithm>
39+
#include <set>
40+
3841
using namespace llvm;
3942
using namespace genx;
4043

@@ -208,7 +211,7 @@ Alignment AlignmentInfo::get(Value *V)
208211
// Handle the case of reading a scalar from element of a vector, as
209212
// a trunc from i32 to i16 is lowered to a bitcast to v2i16 then a
210213
// rdregion.
211-
Region R(WorkInst, BaleInfo());
214+
Region R = makeRegionFromBaleInfo(WorkInst, BaleInfo());
212215
if (!R.Indirect && (R.NumElements == 1))
213216
A = getFromInstMap(WorkInst->getOperand(0));
214217
else

‎IGC/VectorCompiler/lib/GenXCodeGen/GenXArgIndirection.cpp

Lines changed: 23 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -141,7 +141,6 @@ SPDX-License-Identifier: MIT
141141
#include "GenXLiveness.h"
142142
#include "GenXModule.h"
143143
#include "GenXNumbering.h"
144-
#include "GenXRegion.h"
145144
#include "GenXSubtarget.h"
146145
#include "GenXUtil.h"
147146

@@ -1188,15 +1187,19 @@ bool GenXArgIndirection::checkIndirectBale(Bale *B, LiveRange *ArgLR,
11881187
case BaleInfo::WRREGION:
11891188
// Check wrregion if its result is coalesced with arg.
11901189
if (Liveness->getLiveRange(bi->Inst) == ArgLR) {
1191-
Region R(bi->Inst, bi->Info);
1190+
Region R = makeRegionFromBaleInfo(bi->Inst, bi->Info);
11921191
if (R.Indirect)
11931192
break; // already indirect
1194-
// Fake up scalar indirect index for the benefit of getLegalSize.
1195-
// It doesn't matter what the value is, as long as it is scalar.
1193+
// Fake up scalar indirect index for the benefit of
1194+
// getLegalRegionSizeForTarget. It doesn't matter what the value is,
1195+
// as long as it is scalar.
11961196
R.Indirect = bi->Inst->getOperand(
11971197
GenXIntrinsic::GenXRegion::WrIndexOperandNum);
1198-
if (R.NumElements != R.getLegalSize(0, /*Allow2D=*/false,
1199-
/*InputNumElements=*/UINT_MAX, ST, Align)) {
1198+
if (R.NumElements != getLegalRegionSizeForTarget(
1199+
*ST, R,
1200+
/*Idx*/ 0,
1201+
/*Allow2D=*/false,
1202+
/*InputNumElements=*/UINT_MAX, Align)) {
12001203
LLVM_DEBUG(dbgs() << "wrregion cannot be indirected: " << R << "\n");
12011204
return false;
12021205
}
@@ -1205,18 +1208,25 @@ bool GenXArgIndirection::checkIndirectBale(Bale *B, LiveRange *ArgLR,
12051208
case BaleInfo::RDREGION:
12061209
// Check rdregion if its input is coalesced with arg.
12071210
if (Liveness->getLiveRange(bi->Inst->getOperand(0)) == ArgLR) {
1208-
Region R(bi->Inst, bi->Info);
1211+
Region R = makeRegionFromBaleInfo(bi->Inst, bi->Info);
12091212
if (R.Indirect)
12101213
break; // already indirect
1211-
// Fake up scalar indirect index for the benefit of getLegalSize.
1212-
// It doesn't matter what the value is, as long as it is scalar.
1214+
// Fake up scalar indirect index for the benefit of
1215+
// getLegalRegionSizeForTarget. It doesn't matter what the value is,
1216+
// as long as it is scalar.
12131217
R.Indirect = bi->Inst->getOperand(
12141218
GenXIntrinsic::GenXRegion::RdIndexOperandNum);
1215-
if (R.NumElements != R.getLegalSize(0, /*Allow2D=*/true,
1216-
/*InputNumElements=*/UINT_MAX, ST, Align)) {
1219+
if (R.NumElements != getLegalRegionSizeForTarget(
1220+
*ST, R,
1221+
/*Idx*/ 0,
1222+
/*Allow2D=*/true,
1223+
/*InputNumElements=*/UINT_MAX, Align)) {
12171224
LLVM_DEBUG(dbgs() << "rdregion cannot be indirected: " << R << "\n";
1218-
dbgs() << R.getLegalSize(0, /*Allow2D=*/true,
1219-
/*InputNumElements=*/UINT_MAX, ST, Align) << "\n");
1225+
dbgs() << getLegalRegionSizeForTarget(
1226+
*ST, R, /*Idx*/ 0,
1227+
/*Allow2D=*/true,
1228+
/*InputNumElements=*/UINT_MAX, Align)
1229+
<< "\n");
12201230
return false;
12211231
}
12221232
}

‎IGC/VectorCompiler/lib/GenXCodeGen/GenXBaling.cpp

Lines changed: 10 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -17,9 +17,8 @@ SPDX-License-Identifier: MIT
1717
#include "GenXConstants.h"
1818
#include "GenXIntrinsics.h"
1919
#include "GenXLiveness.h"
20-
#include "GenXRegion.h"
2120
#include "GenXUtil.h"
22-
#include "Probe/Assertion.h"
21+
2322
#include "llvm/ADT/DepthFirstIterator.h"
2423
#include "llvm/Analysis/CFG.h"
2524
#include "llvm/Analysis/InstructionSimplify.h"
@@ -41,6 +40,8 @@ SPDX-License-Identifier: MIT
4140

4241
#include "llvmWrapper/IR/DerivedTypes.h"
4342

43+
#include "Probe/Assertion.h"
44+
4445
// Part of the bodge to allow abs to bale in to sext/zext. This needs to be set
4546
// to some arbitrary value that does not clash with any
4647
// GenXIntrinsicInfo::MODIFIER_* value.
@@ -495,7 +496,7 @@ bool GenXBaling::operandCanBeBaled(
495496
(IID != GenXIntrinsic::genx_dpasw) &&
496497
(IID != GenXIntrinsic::genx_dpas_nosrc0) &&
497498
(IID != GenXIntrinsic::genx_dpasw_nosrc0));
498-
Region RdR(Opnd, BaleInfo());
499+
Region RdR = makeRegionFromBaleInfo(Opnd, BaleInfo());
499500
if (!isRegionOKForIntrinsic(AI.Info, RdR, CanSplitBale))
500501
return false;
501502

@@ -509,7 +510,7 @@ bool GenXBaling::operandCanBeBaled(
509510
for (auto U : Opnd->users())
510511
if (isa<BitCastInst>(U))
511512
return false;
512-
Region R(cast<CallInst>(Opnd), BaleInfo());
513+
Region R = makeRegionFromBaleInfo(cast<CallInst>(Opnd), BaleInfo());
513514
if (R.Indirect)
514515
return false;
515516
}
@@ -608,7 +609,8 @@ void GenXBaling::processWrRegion(Instruction *Inst)
608609
V = nullptr;
609610
}
610611

611-
if (V && isBalableNewValueIntoWrr(V, Region(Inst, BaleInfo())) &&
612+
if (V &&
613+
isBalableNewValueIntoWrr(V, makeRegionFromBaleInfo(Inst, BaleInfo())) &&
612614
isSafeToMove(V, V, Inst)) {
613615
LLVM_DEBUG(llvm::dbgs()
614616
<< __FUNCTION__ << " setting operand #" << OperandNum
@@ -1608,8 +1610,8 @@ void GenXBaling::processTwoAddrSend(CallInst *CI)
16081610
if (CI->use_begin()->getOperandNo()
16091611
!= GenXIntrinsic::GenXRegion::NewValueOperandNum)
16101612
return;
1611-
Region RdR(Rd, BaleInfo());
1612-
Region WrR(Wr, BaleInfo());
1613+
Region RdR = genx::makeRegionFromBaleInfo(Rd, BaleInfo());
1614+
Region WrR = genx::makeRegionFromBaleInfo(Wr, BaleInfo());
16131615
if (RdR != WrR || RdR.Indirect || WrR.Mask)
16141616
return;
16151617
if (!isValueRegionOKForRaw(Wr, /*IsWrite=*/true, ST))
@@ -2293,7 +2295,7 @@ bool GenXBaling::prologue(Function *F) {
22932295

22942296
// Skip if this region write is indirect as
22952297
// this would result an indirect read.
2296-
Region R(Inst, BaleInfo());
2298+
Region R = makeRegionFromBaleInfo(Inst, BaleInfo());
22972299
if (R.Indirect)
22982300
continue;
22992301

‎IGC/VectorCompiler/lib/GenXCodeGen/GenXBaling.h

Lines changed: 5 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -215,8 +215,10 @@ SPDX-License-Identifier: MIT
215215
#include "FunctionGroup.h"
216216
#include "GenX.h"
217217
#include "GenXAlignmentInfo.h"
218-
#include "GenXRegion.h"
219218
#include "GenXSubtarget.h"
219+
220+
#include "vc/Utils/GenX/Region.h"
221+
220222
#include "IgnoreRAUWValueMap.h"
221223
#include "Probe/Assertion.h"
222224
#include "llvm/ADT/Hashing.h"
@@ -437,7 +439,7 @@ class GenXBaling {
437439
static bool isBalableIndexOr(Value *V);
438440
// isBalableNewValueIntoWrr: check whether the new val operand can
439441
// be baled into wrr instruction
440-
bool isBalableNewValueIntoWrr(Value *V, const genx::Region &WrrR);
442+
bool isBalableNewValueIntoWrr(Value *V, const Region &WrrR);
441443

442444
static bool isHighCostBaling(uint16_t Type, Instruction *Inst);
443445
// Debug dump/print
@@ -474,7 +476,7 @@ class GenXBaling {
474476
bool operandCanBeBaled(Instruction *Inst, unsigned OperandNum, int ModType,
475477
unsigned ArgInfoBits);
476478

477-
bool isRegionOKForIntrinsic(unsigned ArgInfoBits, const genx::Region &R,
479+
bool isRegionOKForIntrinsic(unsigned ArgInfoBits, const Region &R,
478480
bool CanSplitBale);
479481
bool isSafeToMove(Instruction *Op, Instruction *From, Instruction *To);
480482

‎IGC/VectorCompiler/lib/GenXCodeGen/GenXCategory.cpp

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -123,7 +123,6 @@ SPDX-License-Identifier: MIT
123123
#include "GenXIntrinsics.h"
124124
#include "GenXLiveness.h"
125125
#include "GenXModule.h"
126-
#include "GenXRegion.h"
127126
#include "GenXTargetMachine.h"
128127
#include "GenXUtil.h"
129128

‎IGC/VectorCompiler/lib/GenXCodeGen/GenXCisaBuilder.cpp

Lines changed: 9 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -26,18 +26,17 @@ SPDX-License-Identifier: MIT
2626
//===----------------------------------------------------------------------===//
2727

2828
#include "GenX.h"
29-
#include "vc/Support/BackendConfig.h"
3029
#include "GenXDebugInfo.h"
3130
#include "GenXGotoJoin.h"
3231
#include "GenXIntrinsics.h"
3332
#include "GenXPressureTracker.h"
34-
#include "GenXRegion.h"
3533
#include "GenXSubtarget.h"
3634
#include "GenXTargetMachine.h"
3735
#include "GenXUtil.h"
3836
#include "GenXVisaRegAlloc.h"
3937

4038
#include "vc/GenXOpts/Utils/KernelInfo.h"
39+
#include "vc/Support/BackendConfig.h"
4140
#include "vc/Utils/GenX/Printf.h"
4241

4342
#include "llvm/GenXIntrinsics/GenXIntrinsicInst.h"
@@ -1751,7 +1750,7 @@ GenXKernelBuilder::createDestination(Value *Dest, genx::Signedness Signed,
17511750
}
17521751

17531752
// Write the vISA general operand with region:
1754-
Region R(DstDesc.WrRegion, DstDesc.WrRegionBI);
1753+
Region R = makeRegionFromBaleInfo(DstDesc.WrRegion, DstDesc.WrRegionBI);
17551754

17561755
if (SignedRes)
17571756
*SignedRes = RegAlloc->getSigned(Reg);
@@ -2125,7 +2124,7 @@ VISA_VectorOpnd *GenXKernelBuilder::createSource(Value *V, Signedness Signed,
21252124
else if (Signed == DONTCARESIGNED)
21262125
Signed = SIGNED;
21272126
// Write the vISA general operand with region.
2128-
Region R(Inst, Baling->getBaleInfo(Inst));
2127+
Region R = makeRegionFromBaleInfo(Inst, Baling->getBaleInfo(Inst));
21292128
if (Offset)
21302129
R.Offset = *Offset;
21312130
if (R.NumElements == 1)
@@ -2249,7 +2248,7 @@ std::string GenXKernelBuilder::createInlineAsmDestinationOperand(
22492248
IGC_ASSERT(!Reg || Reg->Category == RegCategory::GENERAL);
22502249

22512250
// Write the vISA general operand with region:
2252-
Region R(DstDesc.WrRegion, DstDesc.WrRegionBI);
2251+
Region R = makeRegionFromBaleInfo(DstDesc.WrRegion, DstDesc.WrRegionBI);
22532252

22542253
return createInlineAsmOperand(Reg, &R, true /*IsDst*/, Signed, Ty, Mod);
22552254
}
@@ -2302,7 +2301,7 @@ std::string GenXKernelBuilder::createInlineAsmSourceOperand(
23022301
if (Signed == DONTCARESIGNED)
23032302
Signed = SIGNED;
23042303
// Write the vISA general operand with region.
2305-
Region R(Inst, Baling->getBaleInfo(Inst));
2304+
Region R = makeRegionFromBaleInfo(Inst, Baling->getBaleInfo(Inst));
23062305
if (R.NumElements == 1)
23072306
R.VStride = 0;
23082307
if (R.Width == 1)
@@ -4793,7 +4792,7 @@ void GenXKernelBuilder::deduceRegion(Region *R, bool IsDest,
47934792
R->IndirectAddrOffset = 0;
47944793
if (GenXIntrinsic::isRdRegion(R->Indirect)) {
47954794
auto AddrRdR = cast<Instruction>(R->Indirect);
4796-
Region AddrR(AddrRdR, BaleInfo());
4795+
Region AddrR = makeRegionFromBaleInfo(AddrRdR, BaleInfo());
47974796
IGC_ASSERT_MESSAGE(!AddrR.Indirect,
47984797
"cannot have address rdregion that is indirect");
47994798
R->IndirectAddrOffset =
@@ -4960,7 +4959,7 @@ void GenXKernelBuilder::addWriteRegionLifetimeStartInst(Instruction *WrRegion) {
49604959
TotalNumElements = VT->getNumElements();
49614960
Instruction *ThisWr = WrRegion;
49624961
for (;;) {
4963-
Region R(ThisWr, BaleInfo());
4962+
Region R = makeRegionFromBaleInfo(ThisWr, BaleInfo());
49644963
if (R.Indirect)
49654964
break;
49664965
if ((unsigned)R.Offset != NumElementsSoFar * R.ElementBytes)
@@ -5452,7 +5451,7 @@ VISA_RawOpnd *GenXKernelBuilder::createRawSourceOperand(const Instruction *Inst,
54525451
bool Baled = Baling->getBaleInfo(Inst).isOperandBaled(OperandNum);
54535452
if (Baled) {
54545453
Instruction *RdRegion = cast<Instruction>(V);
5455-
Region R(RdRegion, BaleInfo());
5454+
Region R = makeRegionFromBaleInfo(RdRegion, BaleInfo());
54565455
ByteOffset = R.Offset;
54575456
V = RdRegion->getOperand(0);
54585457
}
@@ -5485,7 +5484,7 @@ GenXKernelBuilder::createRawDestination(Value *V, const DstOpndDesc &DstDesc,
54855484
unsigned ByteOffset = 0;
54865485
if (DstDesc.WrRegion) {
54875486
V = DstDesc.WrRegion;
5488-
Region R(DstDesc.WrRegion, BaleInfo());
5487+
Region R = makeRegionFromBaleInfo(DstDesc.WrRegion, BaleInfo());
54895488
ByteOffset = R.Offset;
54905489
}
54915490
Type *OverrideType = nullptr;

‎IGC/VectorCompiler/lib/GenXCodeGen/GenXCoalescing.cpp

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -170,7 +170,6 @@ SPDX-License-Identifier: MIT
170170
#include "GenXLiveness.h"
171171
#include "GenXModule.h"
172172
#include "GenXNumbering.h"
173-
#include "GenXRegion.h"
174173
#include "GenXSubtarget.h"
175174
#include "GenXTargetMachine.h"
176175
#include "GenXUtil.h"

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