Skip to content

Commit 317e81f

Browse files
dlei6gigcbot
dlei6g
authored and
igcbot
committed
Add new implicit args intrinsics support
The following new implicit arg intrinsics are supported: GenISA_getPrivateBase GenISA_getStageInGridOrigin GenISA_getStageInGridSize GenISA_getSyncBuffer
1 parent 534cbd3 commit 317e81f

File tree

6 files changed

+54
-25
lines changed

6 files changed

+54
-25
lines changed

‎IGC/AdaptorCommon/ImplicitArgs.cpp

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -38,7 +38,7 @@ static const std::vector<ImplicitArg> IMPLICIT_ARGS = {
3838

3939
ImplicitArg(ImplicitArg::CONSTANT_BASE, "constBase", ImplicitArg::CONSTPTR, WIAnalysis::UNIFORM_GLOBAL, 1, ImplicitArg::ALIGN_PTR, true),
4040
ImplicitArg(ImplicitArg::GLOBAL_BASE, "globalBase", ImplicitArg::GLOBALPTR, WIAnalysis::UNIFORM_GLOBAL, 1, ImplicitArg::ALIGN_PTR, true),
41-
ImplicitArg(ImplicitArg::PRIVATE_BASE, "privateBase", ImplicitArg::PRIVATEPTR, WIAnalysis::UNIFORM_GLOBAL, 1, ImplicitArg::ALIGN_PTR, true),
41+
ImplicitArg(ImplicitArg::PRIVATE_BASE, "privateBase", ImplicitArg::PRIVATEPTR, WIAnalysis::UNIFORM_GLOBAL, 1, ImplicitArg::ALIGN_PTR, true, GenISAIntrinsic::GenISA_getPrivateBase),
4242
ImplicitArg(ImplicitArg::PRINTF_BUFFER, "printfBuffer", ImplicitArg::GLOBALPTR, WIAnalysis::UNIFORM_GLOBAL, 1, ImplicitArg::ALIGN_PTR, true),
4343

4444
ImplicitArg(ImplicitArg::BUFFER_OFFSET, "bufferOffset", ImplicitArg::INT, WIAnalysis::UNIFORM_GLOBAL, 1, ImplicitArg::ALIGN_DWORD, true),
@@ -84,10 +84,10 @@ static const std::vector<ImplicitArg> IMPLICIT_ARGS = {
8484
ImplicitArg(ImplicitArg::LOCAL_MEMORY_STATELESS_WINDOW_SIZE, "localMemStatelessWindowSize", ImplicitArg::INT, WIAnalysis::UNIFORM_GLOBAL, 1, ImplicitArg::ALIGN_DWORD, true),
8585
ImplicitArg(ImplicitArg::PRIVATE_MEMORY_STATELESS_SIZE, "PrivateMemStatelessSize", ImplicitArg::INT, WIAnalysis::UNIFORM_GLOBAL, 1, ImplicitArg::ALIGN_DWORD, true),
8686

87-
ImplicitArg(ImplicitArg::STAGE_IN_GRID_ORIGIN, "stageInGridOrigin", ImplicitArg::INT, WIAnalysis::UNIFORM_GLOBAL, 3, ImplicitArg::ALIGN_GRF, true),
88-
ImplicitArg(ImplicitArg::STAGE_IN_GRID_SIZE, "stageInGridSize", ImplicitArg::INT, WIAnalysis::UNIFORM_GLOBAL, 3, ImplicitArg::ALIGN_GRF, true),
87+
ImplicitArg(ImplicitArg::STAGE_IN_GRID_ORIGIN, "stageInGridOrigin", ImplicitArg::INT, WIAnalysis::UNIFORM_GLOBAL, 3, ImplicitArg::ALIGN_GRF, true, GenISAIntrinsic::GenISA_getStageInGridOrigin),
88+
ImplicitArg(ImplicitArg::STAGE_IN_GRID_SIZE, "stageInGridSize", ImplicitArg::INT, WIAnalysis::UNIFORM_GLOBAL, 3, ImplicitArg::ALIGN_GRF, true, GenISAIntrinsic::GenISA_getStageInGridSize),
8989

90-
ImplicitArg(ImplicitArg::SYNC_BUFFER, "syncBuffer", ImplicitArg::GLOBALPTR, WIAnalysis::UNIFORM_GLOBAL, 1, ImplicitArg::ALIGN_PTR, false),
90+
ImplicitArg(ImplicitArg::SYNC_BUFFER, "syncBuffer", ImplicitArg::GLOBALPTR, WIAnalysis::UNIFORM_GLOBAL, 1, ImplicitArg::ALIGN_PTR, false, GenISAIntrinsic::GenISA_getSyncBuffer),
9191

9292
ImplicitArg(ImplicitArg::BINDLESS_OFFSET, "bindlessOffset", ImplicitArg::INT, WIAnalysis::UNIFORM_GLOBAL, 1, ImplicitArg::ALIGN_DWORD, true),
9393
};

‎IGC/Compiler/CISACodeGen/EmitVISAPass.cpp

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -9110,6 +9110,10 @@ void EmitPass::EmitGenIntrinsicMessage(llvm::GenIntrinsicInst* inst)
91109110
case GenISAIntrinsic::GenISA_getLocalID_X:
91119111
case GenISAIntrinsic::GenISA_getLocalID_Y:
91129112
case GenISAIntrinsic::GenISA_getLocalID_Z:
9113+
case GenISAIntrinsic::GenISA_getPrivateBase:
9114+
case GenISAIntrinsic::GenISA_getStageInGridOrigin:
9115+
case GenISAIntrinsic::GenISA_getStageInGridSize:
9116+
case GenISAIntrinsic::GenISA_getSyncBuffer:
91139117
emitImplicitArgIntrinsic(inst);
91149118
break;
91159119
case GenISAIntrinsic::GenISA_dummyInst:

‎IGC/Compiler/CISACodeGen/WIAnalysis.cpp

Lines changed: 9 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1324,7 +1324,11 @@ WIAnalysis::WIDependancy WIAnalysisRunner::calculate_dep(const CallInst* inst)
13241324
GII_id == GenISAIntrinsic::GenISA_getEnqueuedLocalSize ||
13251325
GII_id == GenISAIntrinsic::GenISA_getLocalID_X ||
13261326
GII_id == GenISAIntrinsic::GenISA_getLocalID_Y ||
1327-
GII_id == GenISAIntrinsic::GenISA_getLocalID_Z)
1327+
GII_id == GenISAIntrinsic::GenISA_getLocalID_Z ||
1328+
GII_id == GenISAIntrinsic::GenISA_getPrivateBase ||
1329+
GII_id == GenISAIntrinsic::GenISA_getStageInGridOrigin ||
1330+
GII_id == GenISAIntrinsic::GenISA_getStageInGridSize ||
1331+
GII_id == GenISAIntrinsic::GenISA_getSyncBuffer)
13281332
{
13291333
switch (GII_id)
13301334
{
@@ -1355,10 +1359,12 @@ WIAnalysis::WIDependancy WIAnalysisRunner::calculate_dep(const CallInst* inst)
13551359
case GenISAIntrinsic::GenISA_getLocalID_X:
13561360
case GenISAIntrinsic::GenISA_getLocalID_Y:
13571361
case GenISAIntrinsic::GenISA_getLocalID_Z:
1358-
{
1362+
case GenISAIntrinsic::GenISA_getPrivateBase:
1363+
case GenISAIntrinsic::GenISA_getStageInGridOrigin:
1364+
case GenISAIntrinsic::GenISA_getStageInGridSize:
1365+
case GenISAIntrinsic::GenISA_getSyncBuffer:
13591366
return ImplicitArgs::getArgDep(GII_id);
13601367
}
1361-
}
13621368

13631369
if (intrinsic_name == llvm_input ||
13641370
intrinsic_name == llvm_shaderinputvec)

‎IGC/Compiler/Optimizer/OpenCLPasses/PrivateMemory/PrivateMemoryResolution.cpp

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -795,8 +795,8 @@ bool PrivateMemoryResolution::resolveAllocaInstructions(bool privateOnStack)
795795

796796
// Find the implicit argument representing r0 and the private memory base.
797797
Value* r0Val = implicitArgs.getImplicitArgValue(*m_currFunction, ImplicitArg::R0, &Ctx);
798-
Argument* privateMemArg = implicitArgs.getImplicitArg(*m_currFunction, ImplicitArg::PRIVATE_BASE);
799-
// Note: for debugging purposes privateMemArg will be marked as Output to keep its liveness all time
798+
Value* privateMemPtr = implicitArgs.getImplicitArgValue(*m_currFunction, ImplicitArg::PRIVATE_BASE, &Ctx);
799+
// Note: for debugging purposes privateMemPtr will be marked as Output to keep its liveness all time
800800

801801
// Resolve the call
802802

@@ -875,7 +875,7 @@ bool PrivateMemoryResolution::resolveAllocaInstructions(bool privateOnStack)
875875
Value* perLaneOffset = isUniform ? builder.getInt32(0) : simdLaneId;
876876
perLaneOffset = builder.CreateMul(perLaneOffset, ConstantInt::get(typeInt32, bufferSize), VALUE_NAME("perLaneOffset"));
877877
Value* totalOffset = builder.CreateAdd(bufferOffsetForThread, perLaneOffset, VALUE_NAME(pAI->getName() + ".totalOffset"));
878-
Value* privateBufferGEP = builder.CreateGEP(privateMemArg, totalOffset, VALUE_NAME(pAI->getName() + ".privateBufferGEP"));
878+
Value* privateBufferGEP = builder.CreateGEP(privateMemPtr, totalOffset, VALUE_NAME(pAI->getName() + ".privateBufferGEP"));
879879
Value* privateBuffer = builder.CreatePointerCast(privateBufferGEP, pAI->getType(), VALUE_NAME(pAI->getName() + ".privateBuffer"));
880880

881881
auto DbgUses = llvm::FindDbgAddrUses(pAI);

‎IGC/Compiler/Optimizer/OpenCLPasses/WIFuncs/WIFuncResolution.cpp

Lines changed: 5 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -686,11 +686,11 @@ Value* WIFuncResolution::getStageInGridOrigin(CallInst& CI)
686686
// Creates:
687687
// %grid_origin1 = extractelement <3 x i32> %globalSize, i32 %dim
688688
auto F = CI.getParent()->getParent();
689-
Argument* arg = m_implicitArgs.getImplicitArg(*F, ImplicitArg::STAGE_IN_GRID_ORIGIN);
690-
IGC_ASSERT(arg != nullptr);
689+
Value* V = m_implicitArgs.getImplicitArgValue(*F, ImplicitArg::STAGE_IN_GRID_ORIGIN, m_pCtx);
690+
IGC_ASSERT(V != nullptr);
691691

692692
Value* dim = CI.getArgOperand(0);
693-
Instruction* globalSize = ExtractElementInst::Create(arg, dim, "grid_origin", &CI);
693+
Instruction* globalSize = ExtractElementInst::Create(V, dim, "grid_origin", &CI);
694694
updateDebugLoc(&CI, globalSize);
695695

696696
return globalSize;
@@ -726,8 +726,7 @@ Value* WIFuncResolution::getStageInGridSize(CallInst& CI)
726726
}
727727
else
728728
{
729-
Argument* arg = m_implicitArgs.getImplicitArg(*F, ImplicitArg::STAGE_IN_GRID_SIZE);
730-
V = arg;
729+
V = m_implicitArgs.getImplicitArgValue(*F, ImplicitArg::STAGE_IN_GRID_SIZE, m_pCtx);
731730
}
732731

733732
IGC_ASSERT(V != nullptr);
@@ -747,7 +746,7 @@ Value* WIFuncResolution::getSyncBufferPtr(CallInst& CI)
747746
// Creates:
748747
// i8 addrspace(1)* %syncBuffer
749748
auto F = CI.getParent()->getParent();
750-
Argument* syncBuffer = m_implicitArgs.getImplicitArg(*F, ImplicitArg::SYNC_BUFFER);
749+
Value* syncBuffer = m_implicitArgs.getImplicitArgValue(*F, ImplicitArg::SYNC_BUFFER, m_pCtx);
751750

752751
return syncBuffer;
753752
}

‎IGC/GenISAIntrinsics/Intrinsic_definitions.py

Lines changed: 29 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -1106,47 +1106,67 @@
11061106
"GenISA_getPayloadHeader": ["",
11071107
[("anyvector", "result"),
11081108
[],
1109-
"NoMem"]],
1109+
"None"]],
11101110
####################################################################################################
11111111
"GenISA_getWorkDim": ["",
11121112
[("anyint", "result"),
11131113
[],
1114-
"NoMem"]],
1114+
"None"]],
11151115
####################################################################################################
11161116
"GenISA_getNumWorkGroups": ["",
11171117
[("anyvector", "result"),
11181118
[],
1119-
"NoMem"]],
1119+
"None"]],
11201120
####################################################################################################
11211121
"GenISA_getGlobalSize": ["",
11221122
[("anyvector", "result"),
11231123
[],
1124-
"NoMem"]],
1124+
"None"]],
11251125
####################################################################################################
11261126
"GenISA_getLocalSize": ["",
11271127
[("anyvector", "result"),
11281128
[],
1129-
"NoMem"]],
1129+
"None"]],
11301130
####################################################################################################
11311131
"GenISA_getEnqueuedLocalSize": ["",
11321132
[("anyvector", "result"),
11331133
[],
1134-
"NoMem"]],
1134+
"None"]],
11351135
####################################################################################################
11361136
"GenISA_getLocalID_X": ["",
11371137
[("short", "result"),
11381138
[],
1139-
"NoMem"]],
1139+
"None"]],
11401140
####################################################################################################
11411141
"GenISA_getLocalID_Y": ["",
11421142
[("short", "result"),
11431143
[],
1144-
"NoMem"]],
1144+
"None"]],
11451145
####################################################################################################
11461146
"GenISA_getLocalID_Z": ["",
11471147
[("short", "result"),
11481148
[],
1149-
"NoMem"]],
1149+
"None"]],
1150+
####################################################################################################
1151+
"GenISA_getPrivateBase": ["",
1152+
[("anyptr", "result"),
1153+
[],
1154+
"None"]],
1155+
####################################################################################################
1156+
"GenISA_getStageInGridOrigin": ["",
1157+
[("anyvector", "result"),
1158+
[],
1159+
"None"]],
1160+
####################################################################################################
1161+
"GenISA_getStageInGridSize": ["",
1162+
[("anyvector", "result"),
1163+
[],
1164+
"None"]],
1165+
####################################################################################################
1166+
"GenISA_getSyncBuffer": ["",
1167+
[("anyptr", "result"),
1168+
[],
1169+
"None"]],
11501170
####################################################################################################
11511171
"GenISA_getSR0": ["sr0.# the state register",
11521172
[("int", "result"),

0 commit comments

Comments
 (0)