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Jay-Jiewu-Lusys_zuul
Jay-Jiewu-Lu
authored and
sys_zuul
committed
minor refactor
Change-Id: Ib1770c8029b4c26438c3d4d4cd25576f78503f07
1 parent 50b9cb8 commit 376ecf1

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4 files changed

+113
-11
lines changed

4 files changed

+113
-11
lines changed

‎IGC/Compiler/CISACodeGen/CISABuilder.cpp

Lines changed: 34 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -3379,38 +3379,63 @@ namespace IGC
33793379

33803380
VISA_EMask_Ctrl CEncoder::ConvertMaskToVisaType(e_mask mask, bool noMask)
33813381
{
3382+
VISA_EMask_Ctrl emaskRet = vISA_EMASK_M1_NM;
33823383
switch (mask)
33833384
{
33843385
case EMASK_Q1:
33853386
if (m_encoderState.m_secondHalf)
33863387
{
3387-
return noMask ? vISA_EMASK_M5_NM : vISA_EMASK_M5;
3388+
emaskRet = noMask ? vISA_EMASK_M5_NM : vISA_EMASK_M5;
33883389
}
33893390
else
33903391
{
3391-
return noMask ? vISA_EMASK_M1_NM : vISA_EMASK_M1;
3392+
emaskRet = noMask ? vISA_EMASK_M1_NM : vISA_EMASK_M1;
33923393
}
3394+
break;
33933395
case EMASK_Q2:
33943396
if (m_encoderState.m_secondHalf)
33953397
{
3396-
return noMask ? vISA_EMASK_M7_NM : vISA_EMASK_M7;
3398+
emaskRet = noMask ? vISA_EMASK_M7_NM : vISA_EMASK_M7;
33973399
}
33983400
else
33993401
{
3400-
return noMask ? vISA_EMASK_M3_NM : vISA_EMASK_M3;
3402+
emaskRet = noMask ? vISA_EMASK_M3_NM : vISA_EMASK_M3;
34013403
}
3404+
break;
34023405
case EMASK_Q3:
3403-
return noMask ? vISA_EMASK_M5_NM : vISA_EMASK_M5;
3406+
emaskRet = noMask ? vISA_EMASK_M5_NM : vISA_EMASK_M5;
3407+
break;
34043408
case EMASK_Q4:
3405-
return noMask ? vISA_EMASK_M7_NM : vISA_EMASK_M7;
3409+
emaskRet = noMask ? vISA_EMASK_M7_NM : vISA_EMASK_M7;
3410+
break;
34063411
case EMASK_H1:
3407-
return noMask ? vISA_EMASK_M1_NM : vISA_EMASK_M1;
3412+
emaskRet = noMask ? vISA_EMASK_M1_NM : vISA_EMASK_M1;
3413+
break;
34083414
case EMASK_H2:
3409-
return noMask ? vISA_EMASK_M5_NM : vISA_EMASK_M5;
3415+
emaskRet = noMask ? vISA_EMASK_M5_NM : vISA_EMASK_M5;
3416+
break;
3417+
default:
3418+
IGC_ASSERT_MESSAGE(0, "unreachable");
3419+
emaskRet = vISA_EMASK_M1_NM;
3420+
}
3421+
3422+
if (!m_encoderState.m_secondNibble)
3423+
return emaskRet;
3424+
3425+
switch (emaskRet) {
3426+
case vISA_EMASK_M1: return vISA_EMASK_M2;
3427+
case vISA_EMASK_M1_NM: return vISA_EMASK_M2_NM;
3428+
case vISA_EMASK_M3: return vISA_EMASK_M4;
3429+
case vISA_EMASK_M3_NM: return vISA_EMASK_M4_NM;
3430+
case vISA_EMASK_M5: return vISA_EMASK_M6;
3431+
case vISA_EMASK_M5_NM: return vISA_EMASK_M6_NM;
3432+
case vISA_EMASK_M7: return vISA_EMASK_M8;
3433+
case vISA_EMASK_M7_NM: return vISA_EMASK_M8_NM;
34103434
default:
34113435
IGC_ASSERT_MESSAGE(0, "unreachable");
34123436
return vISA_EMASK_M1_NM;
34133437
}
3438+
return vISA_EMASK_M1_NM;
34143439
}
34153440

34163441
VISA_Modifier ConvertModifierToVisaType(e_modifier modifier)
@@ -4351,6 +4376,7 @@ namespace IGC
43514376
m_encoderState.m_SubSpanDestination = false;
43524377
CodeGenContext* context = m_program->GetContext();
43534378
m_encoderState.m_secondHalf = false;
4379+
m_encoderState.m_secondNibble = false;
43544380
m_enableVISAdump = false;
43554381
labelMap.clear();
43564382
labelMap.resize(m_program->entry->size(), nullptr);

‎IGC/Compiler/CISACodeGen/CISABuilder.hpp

Lines changed: 13 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -125,6 +125,7 @@ namespace IGC
125125
bool m_noMask;
126126
bool m_SubSpanDestination;
127127
bool m_secondHalf;
128+
bool m_secondNibble = false;
128129
};
129130

130131
class CEncoder
@@ -353,6 +354,8 @@ namespace IGC
353354
inline bool IsSubSpanDestination();
354355
inline void SetSecondHalf(bool secondHalf);
355356
inline bool IsSecondHalf();
357+
inline void SetSecondNibble(bool secondNibble);
358+
inline bool IsSecondNibble();
356359

357360
void Wait();
358361

@@ -925,6 +928,16 @@ namespace IGC
925928
return m_encoderState.m_secondHalf;
926929
}
927930

931+
inline void CEncoder::SetSecondNibble(bool secondNibble)
932+
{
933+
m_encoderState.m_secondNibble = secondNibble;
934+
}
935+
936+
inline bool CEncoder::IsSecondNibble()
937+
{
938+
return m_encoderState.m_secondNibble;
939+
}
940+
928941
inline bool CEncoder::IsSubSpanDestination()
929942
{
930943
return m_encoderState.m_SubSpanDestination;

‎IGC/Compiler/CISACodeGen/EmitVISAPass.cpp

Lines changed: 59 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -10310,6 +10310,51 @@ void EmitPass::emitInsert(llvm::Instruction* inst)
1031010310
}
1031110311
else
1031210312
{
10313+
// Lower execution size to avoid complains of indirectly addressing across more than two GRFs.
10314+
// One example is below:
10315+
//(W) mov (1|M0) f1.1<1>:uw 0x100:uw
10316+
//(f1.1) mov(16|M0) r[a0.8]<1>:f r63.0 < 0; 1, 0 >:f
10317+
//will be changed to
10318+
//(W) mov (1|M0) f1.1<1>:uw 0x100:uw
10319+
//(f1.1) mov(8|M8) r[a0.8+0x20]<1>:f r63.0 < 0; 1, 0 >:f
10320+
// To avoid complains, we limit the execSizeNew*datatypesize to the same memory size of getMinDispatchMode()
10321+
// In above example, say, getMinDispatchMode()==8, that means the execSizeNew should be 8
10322+
// because 8 * SIZE_DWORD = getMinDispatchMode() * SIZE_DWORD
10323+
// But if datatype is 64bit, then, execSizeNew should be 4
10324+
// because 4 * SIZE_QWORD = getMinDispatchMode() * SIZE_DWORD
10325+
// Changing to simd1 needs more work and might cause extra overhead as well.
10326+
// indirect address, emaskoffset should be offsetted correspondingly
10327+
SIMDMode simdMode = std::min(m_currShader->m_SIMDSize, SIMDMode::SIMD16);
10328+
SIMDMode minDispatchMode = m_currShader->m_Platform->getMinDispatchMode();
10329+
SIMDMode execSizeNew = minDispatchMode;
10330+
bool bWAMultiGRF = false;
10331+
if (m_currShader->m_Platform->enableMultiGRFAccessWA())
10332+
{
10333+
uint32_t dataTypeSize = pElement->getType()->getScalarSizeInBits();
10334+
uint32_t memSizeToUse = numLanes(simdMode) * dataTypeSize / 8;
10335+
uint32_t memSizeMinDisp = numLanes(minDispatchMode) * SIZE_DWORD;
10336+
bWAMultiGRF = (memSizeToUse > memSizeMinDisp);
10337+
if (bWAMultiGRF)
10338+
{
10339+
execSizeNew = lanesToSIMDMode(memSizeMinDisp * 8 / dataTypeSize);
10340+
uint32_t lanesNew = numLanes(execSizeNew);
10341+
int cnt = memSizeToUse / memSizeMinDisp;
10342+
for (int i=1; i<cnt; i++)
10343+
{
10344+
CVariable* pOffset1_2ndHalf = m_currShader->ImmToVariable(memSizeMinDisp * i, ISA_TYPE_UW);
10345+
uint32_t laneIdx = lanesNew * i;
10346+
CVariable* pOffset2_2ndHalf = m_currShader->GetNewAlias(pOffset2, ISA_TYPE_UW, laneIdx * SIZE_WORD, 0);
10347+
m_encoder->SetSrcRegion(0, lanesNew, lanesNew, 1);
10348+
m_encoder->SetSimdSize(execSizeNew);
10349+
m_encoder->SetMask((laneIdx / 8) % 2 ? EMASK_Q2 : EMASK_Q1);
10350+
m_encoder->SetSecondNibble((laneIdx / 4) % 2 ? true : false);
10351+
m_encoder->Add(pOffset2_2ndHalf, pOffset2_2ndHalf, pOffset1_2ndHalf);
10352+
m_encoder->Push();
10353+
}
10354+
m_encoder->SetSecondNibble(false);
10355+
}
10356+
}
10357+
1031310358
int loopCount = (m_currShader->m_dispatchSize == SIMDMode::SIMD32 && m_currShader->m_numberInstance == 1) ? 2 : 1;
1031410359
for (int i = 0; i < loopCount; ++i)
1031510360
{
@@ -10318,7 +10363,6 @@ void EmitPass::emitInsert(llvm::Instruction* inst)
1031810363
// explicitly set second half as we are manually splitting
1031910364
m_encoder->SetSecondHalf(true);
1032010365
}
10321-
SIMDMode simdMode = std::min(m_currShader->m_SIMDSize, SIMDMode::SIMD16);
1032210366
CVariable* pDstArrElm = m_currShader->GetNewAddressVariable(
1032310367
numLanes(simdMode),
1032410368
m_destination->GetType(),
@@ -10355,9 +10399,22 @@ void EmitPass::emitInsert(llvm::Instruction* inst)
1035510399
}
1035610400
m_encoder->SetSrcRegion(0, 0, 1, 0);
1035710401
m_encoder->SetDstSubReg(lane);
10358-
m_encoder->SetSimdSize(simdMode);
10402+
if(bWAMultiGRF)
10403+
{
10404+
m_encoder->SetMask((lane / 8) % 2 ? EMASK_Q2 : EMASK_Q1);
10405+
if (execSizeNew == SIMDMode::SIMD4)
10406+
{
10407+
m_encoder->SetSecondNibble((lane / 4) % 2 ? true : false);
10408+
}
10409+
m_encoder->SetSimdSize(execSizeNew);
10410+
}
10411+
else
10412+
{
10413+
m_encoder->SetSimdSize(simdMode);
10414+
}
1035910415
m_encoder->Copy(pDstArrElm, pElemVar);
1036010416
m_encoder->Push();
10417+
m_encoder->SetSecondNibble(false);
1036110418
}
1036210419
}
1036310420
}

‎IGC/Compiler/CISACodeGen/Platform.hpp

Lines changed: 7 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -569,7 +569,13 @@ bool WaEnableA64WA() const
569569
return false;
570570
}
571571

572-
const SCompilerHwCaps& GetCaps() { return m_caps; }
572+
//Only enable this WA for TGLLP+ because, in pre TGLLP projects, smov was replaced with two instructions which caused performance penalty.
573+
bool enableMultiGRFAccessWA() const
574+
{
575+
return (m_platformInfo.eProductFamily >= IGFX_TIGERLAKE_LP);
576+
}
577+
578+
const SCompilerHwCaps& GetCaps() { return m_caps; }
573579
};
574580

575581
}//namespace IGC

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