Always use bufferOffset for unaligned pointers

When a pointer to SVM is not aligned to 4 bytes, Neo aligns it and stores
a difference between aligned and unaligned pointer into `bufferOffset`
argument, so that IGC can correctly access the memory. Neo must align
the pointer since hardware expects surface state base address to be
aligned to 4 bytes.

This change prevents optimizing `bufferOffset` argument usage out when
IGC cannot assure that a pointer is 4 bytes aligned.

Author: aratajew

IGC/Compiler/CISACodeGen/OpenCLOptions.cpp

@@ -86,11 +86,6 @@ void InternalOptions::parseOptions(const char* internalOpts)
         IntelHasPositivePointerOffset = true;
     }
 
-    if (internalOptions.hasArg(OPT_has_subdw_aligned_ptr_arg_common))
-    {
-        IntelHasSubDWAlignedPtrArg = true;
-    }
-
     if (internalOptions.hasArg(OPT_disable_a64wa_common))
     {
         IntelDisableA64WA = true;

IGC/Compiler/CISACodeGen/OpenCLOptions.hpp

@@ -41,10 +41,6 @@ class InternalOptions
     bool IntelHasPositivePointerOffset              = false;
     bool IntelHasBufferOffsetArg                    = false;
     bool IntelBufferOffsetArgOptional               = true;
-    bool IntelHasSubDWAlignedPtrArg                 = false;
-    // default: false, meaning kernel's sub-DW ptrArgs (char*, short*) are DW-aligned.
-    // This default is stronger than the natural alignment implied by char*/short*. But
-    // for historical reason, we have this.
 
     bool replaceGlobalOffsetsByZero                 = false;
     bool IntelEnablePreRAScheduling                 = true;

IGC/Compiler/Optimizer/OpenCLPasses/StatelessToStateful/StatelessToStateful.cpp

@@ -19,6 +19,7 @@ SPDX-License-Identifier: MIT
 #include <llvm/IR/Instructions.h>
 #include <llvm/IR/GetElementPtrTypeIterator.h>
 #include <llvm/Analysis/ValueTracking.h>
+#include <llvm/Transforms/Utils/Local.h>
 #include "common/LLVMWarningsPop.hpp"
 #include <string>
 #include "Probe/Assertion.h"
@@ -132,7 +133,6 @@ StatelessToStateful::StatelessToStateful()
     : FunctionPass(ID),
     m_hasBufferOffsetArg(false),
     m_hasOptionalBufferOffsetArg(false),
-    m_hasSubDWAlignedPtrArg(false),
     m_hasPositivePointerOffset(false),
     m_ACT(nullptr),
     m_pImplicitArgs(nullptr),
@@ -175,13 +175,11 @@ bool StatelessToStateful::runOnFunction(llvm::Function& F)
     m_hasOptionalBufferOffsetArg = (m_hasBufferOffsetArg &&
         (IGC_IS_FLAG_ENABLED(EnableOptionalBufferOffset) || modMD->compOpt.BufferOffsetArgOptional));
 
-    m_hasSubDWAlignedPtrArg = (IGC_IS_FLAG_ENABLED(UseSubDWAlignedPtrArg) || modMD->compOpt.HasSubDWAlignedPtrArg);
-
     m_hasPositivePointerOffset = (IGC_IS_FLAG_ENABLED(SToSProducesPositivePointer) || modMD->compOpt.HasPositivePointerOffset);
 
     m_pImplicitArgs = new ImplicitArgs(F, pMdUtils);
-    CodeGenContext* ctx = getAnalysis<CodeGenContextWrapper>().getCodeGenContext();
-    m_pKernelArgs = new KernelArgs(F, &(F.getParent()->getDataLayout()), pMdUtils, modMD, ctx->platform.getGRFSize());
+    m_ctx = static_cast<OpenCLProgramContext*>(getAnalysis<CodeGenContextWrapper>().getCodeGenContext());
+    m_pKernelArgs = new KernelArgs(F, &(F.getParent()->getDataLayout()), pMdUtils, modMD, m_ctx->platform.getGRFSize());
 
     findPromotableInstructions();
     promote();
@@ -428,10 +426,28 @@ bool StatelessToStateful::pointerIsPositiveOffsetFromKernelArgument(
         // guarantted to be DW-aligned.)
         //
         // Note that implicit arg is always aligned.
-        bool isAlignedPointee =
-            (!m_hasSubDWAlignedPtrArg || arg->isImplicitArg())
-            ? true
-            : (getPointeeAlign(DL, base) >= 4);
+        bool isAlignedPointee = false;
+        if (arg->isImplicitArg())
+        {
+            isAlignedPointee = true;
+        }
+        else
+        {
+            isAlignedPointee = getPointeeAlign(DL, base) >= 4 ||
+                // The intent of getKnownAlignment below is to check if any llvm.assume intrinsic provides
+                // a hint about the base pointer alignment
+                getKnownAlignment((Value*)arg->getArg(), *DL, F->getEntryBlock().getFirstNonPHI(), AC) >= 4;
+        }
+
+        // When compiling with patch tokens, always assume that the address
+        // is aligned. This is a workaround for old OneMKL Releases. Assuming
+        // that the address is not aligned leads to using bufferOffset implicit
+        // argument. The additional argument confuses compatibility check in OneMKL
+        // and forces it to make a fallback to a different kernels.
+        // TODO: Remove below if statement as soon as support for old OneMKL
+        //       versions is dropped.
+        if (!m_ctx->enableZEBinary())
+            isAlignedPointee = true;
 
         // special handling
         if (m_supportNonGEPPtr && gep == nullptr && !arg->isImplicitArg())

IGC/Compiler/Optimizer/OpenCLPasses/StatelessToStateful/StatelessToStateful.hpp

@@ -10,6 +10,7 @@ SPDX-License-Identifier: MIT
 
 #include "AdaptorCommon/ImplicitArgs.hpp"
 #include "Compiler/Optimizer/OpenCLPasses/KernelArgs/KernelArgs.hpp"
+#include "Compiler/CISACodeGen/OpenCLKernelCodeGen.hpp"
 #include "Compiler/MetaDataUtilsWrapper.h"
 #include "common/LLVMWarningsPush.hpp"
 #include <llvm/Pass.h>
@@ -151,11 +152,6 @@ namespace IGC
         // can be on or off, which is indicated by this boolean flag.
         bool       m_hasOptionalBufferOffsetArg;
 
-        // For historic reason, kernel ptrArgs, such as char*, short*, are assumed to
-        // be aligned on DW (which is stronger than what OCL's natural alignment) in this
-        // stateful optimization.  If this is not a case, this arg should be set to true!
-        bool       m_hasSubDWAlignedPtrArg;
-
         // When true, every messages that are in ptrArg + offset will have offset >= 0.
         bool       m_hasPositivePointerOffset;
 
@@ -171,6 +167,7 @@ namespace IGC
                 : nullptr);
         }
 
+        OpenCLProgramContext* m_ctx;
         ImplicitArgs* m_pImplicitArgs;
         KernelArgs* m_pKernelArgs;
         ArgInfoMap   m_argsInfo;

IGC/Compiler/tests/StatelessToStateful/bufferOffset/char_pointer_argument.ll

@@ -0,0 +1,43 @@
+;=========================== begin_copyright_notice ============================
+;
+; Copyright (C) 2023 Intel Corporation
+;
+; SPDX-License-Identifier: MIT
+;
+;============================ end_copyright_notice =============================
+
+; RUN: igc_opt %s -S -o - -serialize-igc-metadata -igc-stateless-to-stateful-resolution -platformpvc | FileCheck %s
+
+target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v16:16:16-v24:32:32-v32:32:32-v48:64:64-v64:64:64-v96:128:128-v128:128:128-v192:256:256-v256:256:256-v512:512:512-v1024:1024:1024-n8:16:32"
+
+define spir_kernel void @test(i8 addrspace(1)* %dst, i32 %bufferOffset) {
+entry:
+  ; CHECK: %[[OFFSET:[0-9]+]] = add i32 %bufferOffset, 3
+  ; CHECK: %[[PTR:[0-9]+]] = inttoptr i32 %[[OFFSET]] to i8 addrspace(131072)*
+  ; CHECK: store i8 0, i8 addrspace(131072)* %[[PTR]], align 1
+  %ptr = getelementptr inbounds i8, i8 addrspace(1)* %dst, i64 3
+  store i8 0, i8 addrspace(1)* %ptr, align 1
+  ret void
+}
+
+!IGCMetadata = !{!0}
+!igc.functions = !{!1}
+
+!0 = !{!"ModuleMD", !5, !16}
+!1 = !{void (i8 addrspace(1)*, i32)* @test, !2}
+!2 = !{!3, !14}
+!3 = !{!"function_type", i32 0}
+!4 = !{}
+!5 = !{!"FuncMD", !6, !7}
+!6 = !{!"FuncMDMap[0]", void (i8 addrspace(1)*, i32)* @test}
+!7 = !{!"FuncMDValue[0]", !8}
+!8 = !{!"resAllocMD", !9}
+!9 = !{!"argAllocMDList", !10}
+!10 = !{!"argAllocMDListVec[0]", !11}
+!11 = !{!"type", i32 1}
+!12 = !{!"extensionType", i32 -1}
+!13 = !{!"indexType", i32 0}
+!14 = !{!"implicit_arg_desc", !15}
+!15 = !{i32 14}
+!16 = !{!"compOpt", !17}
+!17 = !{!"HasBufferOffsetArg", i1 true}

IGC/OCLFE/igd_fcl_mcl/source/clang_tb.cpp

@@ -1348,8 +1348,6 @@ namespace TC
                             (strcmp(pParam, "-ze-opt-has-buffer-offset-arg") == 0) || //temporary options
                             (strcmp(pParam, "-cl-intel-buffer-offset-arg-required") == 0) || //temporary options
                             (strcmp(pParam, "-ze-opt-buffer-offset-arg-required") == 0) || //temporary options
-                            (strcmp(pParam, "-cl-intel-has-subDW-aligned-ptr-arg") == 0) || //temporary options
-                            (strcmp(pParam, "-ze-opt-has-subDW-aligned-ptr-arg") == 0) || //temporary options
                             (strcmp(pParam, "-cl-force-global-mem-allocation") == 0) || // temp
                             (strcmp(pParam, "-ze-force-global-mem-allocation") == 0) || // temp
                             (strcmp(pParam, "-cl-no-local-to-generic") == 0) || // temp

IGC/Options/include/igc/Options/IGCInternalOptions.td

@@ -39,9 +39,6 @@ defm buffer_offset_arg_required : CommonFlag<"buffer-offset-arg-required">;
 // -cl-intel-has-positive-pointer-offset, -ze-opt-has-positive-pointer-offset
 defm has_positive_pointer_offset : CommonFlag<"has-positive-pointer-offset">;
 
-// -cl-intel-has-subDW-aligned-ptr-arg, -ze-opt-has-subDW-aligned-ptr-arg
-defm has_subdw_aligned_ptr_arg : CommonFlag<"has-subDW-aligned-ptr-arg">;
-
 // -cl-intel-disable-a64WA
 defm disable_a64wa : CommonFlag<"disable-a64WA">;
 

IGC/common/MDFrameWork.h

@@ -394,7 +394,6 @@ namespace IGC
         bool HasPositivePointerOffset                   = false;
         bool HasBufferOffsetArg                         = false;
         bool BufferOffsetArgOptional                    = true;
-        bool HasSubDWAlignedPtrArg                      = false;
         bool replaceGlobalOffsetsByZero                 = false;
         unsigned forcePixelShaderSIMDMode               = 0;
         bool pixelShaderDoNotAbortOnSpill               = false;

IGC/common/igc_flags.h

@@ -304,7 +304,6 @@ DECLARE_IGC_REGKEY(DWORD, DebugInternalSwitch,          0,     "Code pass select
 DECLARE_IGC_REGKEY(bool, SToSProducesPositivePointer,   false, "This key is for StatelessToStateful optimization if the  user knows the pointer offset is postive to the kernel argument.", false)
 DECLARE_IGC_REGKEY(bool, EnableSupportBufferOffset,     false, "[debugging]For StatelessToStateful optimization [OCL], support implicit buffer offset argument (same as -cl-intel-has-buffer-offset-arg).", false)
 DECLARE_IGC_REGKEY(bool, EnableOptionalBufferOffset,    true,  "For StatelessToStateful optimization [OCL], if true, make buffer offset optional. Valid only if buffer offset is supported.", true)
-DECLARE_IGC_REGKEY(bool, UseSubDWAlignedPtrArg,         false, "[OCL]If set, for kernel pointer arg such as ptr to char or short, the arg is not necessarily DW aligned", false)
 DECLARE_IGC_REGKEY(bool, EnableTestIGCBuiltin,          false, "Enable testing igc builtin (precompiled kernels) using OCL.", false)
 DECLARE_IGC_REGKEY(DWORD, TestIGCPreCompiledFunctions,  0,     "Enable testing for precompiled kernels. [TEST ONLY]", false)
 DECLARE_IGC_REGKEY(bool, EnableCSSIMD32,                false, "Enable computer shader SIMD32 mode, and fall back to lower SIMD when spill", false)

documentation/configuration_flags.md

@@ -307,7 +307,6 @@ $ export IGC_ShaderDumpEnable=1
 | `ShaderOverride` | Will override any LLVM shader with matching name in c:\\Intel\\IGC\\ShaderOverride | - |
 | `ShaderPassDisable` | Disable specific passes eg. '9;17-19;239-;Error Check;ResolveOCLAtomics:2;Dead Code Elimination:3-5;BreakConstantExprPass:7-'<br/>                                                                disable pass 9, disable passes from 17 to 19, disable all passes after 238, disable all occurrences of pass Error Check,<br/>                                                                disable second occurrence of ResolveOCLAtomics, disable pass Dead Code Elimination occurrences from 3 to 5,<br/>                                                                disable all BreakConstantExprPass after his 6 occurrence<br/>                                                                To show a list of pass names and their occurrence set ShaderDisplayAllPassesNames.<br/>                                                                Must be used with ShaderDumpEnableAll flag. | - |
 | `SystemThreadEnable` | This key forces software to create a system thread. The system thread may still be created by software even<br/>                                                                if this control is set to false.The system thread is invoked if either the software requires<br/>                                                                exception handling or if kernel debugging is active and a breakpoint is hit. | - |
-| `UseSubDWAlignedPtrArg` | [OCL]If set, for kernel pointer arg such as ptr to char or short, the arg is not necessarily DW aligned | - |
 | `ld2dmsInstsClubbingThreshold` | Do not club more than these ld2dms insts into the new BB during MCSOpt | - |
 | `manualEnableRSWA` | Enable read suppression WA for the send and indirect access | - |
 ## Shader dumping