Insert move to dbg instruction to help debug

Insert move to dbg instruction to help debug

Author: bcheng0127

IGC/Compiler/CISACodeGen/CISABuilder.cpp

@@ -4805,6 +4805,11 @@ namespace IGC
             SaveOption(vISA_EnableGroupScheduleForBC, true);
         }
 
+        if (IGC_IS_FLAG_ENABLED(CopyA0ToDBG0))
+        {
+            SaveOption(vISA_CopyA0ToDBG0, true);
+        }
+
         if (VISAPlatform == Xe_XeHPSDV && IGC_IS_FLAG_ENABLED(DPASTokenReduction))
         {
             SaveOption(vISA_EnableDPASTokenReduction, true);

IGC/common/igc_flags.h

@@ -270,6 +270,7 @@ DECLARE_IGC_REGKEY(DWORD, GEPLSRThresholdRatio, 100, "Ratio for register pressur
 DECLARE_IGC_REGKEY(bool, EnableGEPLSRToPreheader, true, "Enables reduction to loop's preheader in GEP Loop Strength Reduction pass", false)
 
 DECLARE_IGC_GROUP("Shader debugging")
+DECLARE_IGC_REGKEY(bool, CopyA0ToDBG0,                           false, " Copy a0 used for extended msg descriptor to dbg0 to help debug", false)
 DECLARE_IGC_REGKEY(bool, EnableDebugging,                           false, " Enable shader debugging for release internal", false)
 DECLARE_IGC_REGKEY_BITMASK(GenerateOptionsFile, 0, "Create Options.txt(usually for SIMD related bugs to narrow down shaders), in the shader dump folder.", SHADER_TYPE_MASKS, false)
 DECLARE_IGC_REGKEY(bool, ForceDisableShaderDebugHashCodeInKernel,   false,  "Disable hash code addition to the binary after EOT", false)

visa/BuildIRImpl.cpp

@@ -1855,6 +1855,12 @@ G4_SrcRegRegion *IR_Builder::createScratchExDesc(uint32_t exdesc) {
     createBinOp(G4_add, g4::SIMD1, dst, T251, createImm(exdesc, Type_UD),
                 InstOpt_WriteEnable, true);
   }
+  if (getOption(vISA_CopyA0ToDBG0)) {
+    G4_SrcRegRegion *srcA0 = createSrcRegRegion(exDescDecl, getRegionScalar());
+    G4_DstRegRegion *dstDbg0 =
+        createDst(phyregpool.getDbgReg(), 0, 0, 1, Type_UD);
+    createMov(g4::SIMD1, dstDbg0, srcA0, InstOpt_WriteEnable, true);
+  }
   return createSrcRegRegion(exDescDecl, getRegionScalar());
 }
 
@@ -2192,6 +2198,12 @@ G4_SrcRegRegion *IR_Builder::createBindlessExDesc(uint32_t exdesc) {
     createBinOp(G4_add, g4::SIMD1, dst, T252, createImm(exdesc, Type_UD),
                 InstOpt_WriteEnable, true);
   }
+  if (getOption(vISA_CopyA0ToDBG0)) {
+    G4_SrcRegRegion *srcA0 = createSrcRegRegion(exDescDecl, getRegionScalar());
+    G4_DstRegRegion *dstDbg0 =
+        createDst(phyregpool.getDbgReg(), 0, 0, 1, Type_UD);
+    createMov(g4::SIMD1, dstDbg0, srcA0, InstOpt_WriteEnable | dbgOpt, true);
+  }
   return createSrcRegRegion(exDescDecl, getRegionScalar());
 }
 
@@ -2271,6 +2283,12 @@ G4_InstSend *IR_Builder::createSendInst(G4_Predicate *pred,
       }
     }
 
+    if (getOption(vISA_CopyA0ToDBG0)) {
+      G4_SrcRegRegion *srcA0 = createSrcRegRegion(builtinA0, getRegionScalar());
+      G4_DstRegRegion *dstDbg0 =
+          createDst(phyregpool.getDbgReg(), 0, 0, 1, Type_UD);
+      createMov(g4::SIMD1, dstDbg0, srcA0, InstOpt_WriteEnable, true);
+    }
     descOpnd = createSrcRegRegion(builtinA0, getRegionScalar());
   } else {
     descOpnd = createImm(desc, Type_UD);
@@ -2394,6 +2412,13 @@ IR_Builder::createSplitSendInst(G4_Predicate *pred, G4_DstRegRegion *dst,
   }
 
   if (needsSurfaceMove || needsSamplerMove) {
+    if (getOption(vISA_CopyA0ToDBG0)) {
+      G4_SrcRegRegion *srcA0 = createSrcRegRegion(builtinA0, getRegionScalar());
+      G4_DstRegRegion *dstDbg0 =
+          createDst(phyregpool.getDbgReg(), 0, 0, 1, Type_UD);
+      createMov(g4::SIMD1, dstDbg0, srcA0, InstOpt_WriteEnable, true);
+    }
+
     descOpnd = createSrcRegRegion(builtinA0, getRegionScalar());
   } else {
     descOpnd = createImm(desc, Type_UD);
@@ -2609,6 +2634,12 @@ G4_InstSend *IR_Builder::createLscSendInst(
       }
     }
 
+    if (getOption(vISA_CopyA0ToDBG0)) {
+      G4_SrcRegRegion *srcA0 = createSrcRegRegion(builtinA0Dot2, getRegionScalar());
+      G4_DstRegRegion *dstDbg0 =
+          createDst(phyregpool.getDbgReg(), 0, 0, 1, Type_UD);
+      createMov(g4::SIMD1, dstDbg0, srcA0, InstOpt_WriteEnable, true);
+    }
     exDescOpnd = createSrcRegRegion(builtinA0Dot2, getRegionScalar());
     msgDesc->setSurface(exDescOpnd); // link a0.2 to the send descriptor
   } else if (surface && surface->isImm()) {
@@ -2631,6 +2662,12 @@ G4_InstSend *IR_Builder::createLscSendInst(
       createMov(g4::SIMD1, addrDstOpnd, createImm(imm, Type_UD),
                 InstOpt_WriteEnable, true);
 
+      if (getOption(vISA_CopyA0ToDBG0)) {
+        G4_SrcRegRegion *srcA0 = createSrcRegRegion(builtinA0Dot2, getRegionScalar());
+        G4_DstRegRegion *dstDbg0 =
+            createDst(phyregpool.getDbgReg(), 0, 0, 1, Type_UD);
+        createMov(g4::SIMD1, dstDbg0, srcA0, InstOpt_WriteEnable, true);
+      }
       exDescOpnd = createSrcRegRegion(builtinA0Dot2, getRegionScalar());
       msgDesc->setSurface(exDescOpnd); // link a0.2 to the send descriptor
     } else {
@@ -2712,6 +2749,12 @@ G4_InstSend *IR_Builder::createSplitSendToRenderTarget(
     G4_DstRegRegion *addrDstOpnd = createDstRegRegion(builtinA0, 1);
     createBinOp(G4_add, g4::SIMD1, addrDstOpnd, bti, createImm(desc, Type_UD),
                 InstOpt_WriteEnable, true);
+    if (getOption(vISA_CopyA0ToDBG0)) {
+      G4_SrcRegRegion *srcA0 = createSrcRegRegion(builtinA0, getRegionScalar());
+      G4_DstRegRegion *dstDbg0 =
+          createDst(phyregpool.getDbgReg(), 0, 0, 1, Type_UD);
+      createMov(g4::SIMD1, dstDbg0, srcA0, InstOpt_WriteEnable, true);
+    }
     descOpnd = createSrcRegRegion(builtinA0, getRegionScalar());
   } else {
     descOpnd = createImm(desc, Type_UD);

visa/G4_IR.cpp

@@ -2987,7 +2987,7 @@ bool G4_INST::isOptBarrier() const {
   if (dst) {
     if (dst->isAreg()) {
       if (dst->isNReg() || dst->isSrReg() || dst->isCrReg() || dst->isTmReg() ||
-          dst->isTDRReg()) {
+          dst->isTDRReg() || dst->isDbgReg()) {
         return true;
       }
     }

visa/include/VISAOptionsDefs.h

@@ -94,6 +94,8 @@ DEF_VISA_OPTION(vISA_asmToConsole, ET_BOOL, "-asmToConsole",
 DEF_VISA_OPTION(vISA_DebugOnly, ET_CSTR, "-debug-only", UNUSED, NULL)
 DEF_VISA_OPTION(vISA_DisablePrefetchToL1Cache, ET_BOOL, "-disablePrefetchL1",
                 "Disables L1 cached for prefetch messages", false)
+DEF_VISA_OPTION(vISA_CopyA0ToDBG0, ET_BOOL, "-copyA0ToDBG0",
+                "copy value of a0 used for extend msg descriptor of send to the dbg0 register", false)
 
 //=== Optimization options ===
 DEF_VISA_OPTION(vISA_EnableAlways, ET_BOOL, NULLSTR, UNUSED, true)