Fix pattern matching pass in VC

Write region related transformations require DataLayout to detect
pointer bit width.

Author: vmustya

IGC/VectorCompiler/lib/GenXCodeGen/GenXPatternMatch.cpp

@@ -633,7 +633,7 @@ void GenXPatternMatch::visitICmpInst(ICmpInst &I) {
         BC->setDebugLoc(I.getDebugLoc());
 
         // Create the new rdregion.
-        vc::Region R(BC);
+        vc::Region R(BC, DL);
         R.NumElements = NElts;
         R.Stride = Stride;
         R.Width = NElts;
@@ -2262,7 +2262,7 @@ bool GenXPatternMatch::propagateFoldableRegion(Function *F) {
         if (WII->getOperand(1) != Mul)
           continue;
         auto W = makeRegionFromBaleInfo(WII, BaleInfo());
-        vc::Region V(Mul);
+        vc::Region V(Mul, DL);
         // TODO: Consider the broadcast and similar cases.
         if (!W.isStrictlySimilar(V))
           continue;
@@ -2439,7 +2439,7 @@ bool GenXPatternMatch::simplifyWrRegion(CallInst *Inst) {
       IRBuilder<> B(Inst);
       NewV = B.CreateBitCast(NewV, IGCLLVM::FixedVectorType::get(NewVTy, 1));
     }
-    vc::Region R(Inst->getType());
+    vc::Region R(Inst->getType(), DL);
     R.Width = R.NumElements;
     R.Stride = 0;
     NewV = R.createRdRegion(NewV, "splat", Inst, Inst->getDebugLoc(),
@@ -3446,15 +3446,15 @@ bool GenXPatternMatch::vectorizeConstants(Function *F) {
           IRBuilder<> Builder(Inst);
           unsigned Width = cast<IGCLLVM::FixedVectorType>(ShtAmt[0]->getType())
                                ->getNumElements();
-          vc::Region R(C->getType());
+          vc::Region R(C->getType(), DL);
           R.getSubregion(0, Width);
           Value *Val = UndefValue::get(C->getType());
           Val = R.createWrRegion(Val, Base, "", Inst, Inst->getDebugLoc());
           for (unsigned j = 1; j < (unsigned)ShtAmt.size(); ++j) {
             auto Opc = C->getType()->isFPOrFPVectorTy() ? Instruction::FAdd
                                                         : Instruction::Add;
             auto Input = Builder.CreateBinOp(Opc, Base, ShtAmt[j]);
-            vc::Region R1(C->getType());
+            vc::Region R1(C->getType(), DL);
             R1.getSubregion(Width * j, Width);
             Val = R1.createWrRegion(Val, Input, "", Inst, Inst->getDebugLoc());
           }

IGC/VectorCompiler/test/PatternMatch/WrRegion_optimize.ll

@@ -1,6 +1,6 @@
 ;=========================== begin_copyright_notice ============================
 ;
-; Copyright (C) 2021 Intel Corporation
+; Copyright (C) 2021-2023 Intel Corporation
 ;
 ; SPDX-License-Identifier: MIT
 ;
@@ -20,3 +20,14 @@ define <16 x i32> @test(<64 x i32> %val, <16 x i1> %cond) {
   %3 = tail call <16 x i32> @llvm.genx.wrregioni.v16i32.v16i32.i16.v16i1(<16 x i32> %2, <16 x i32> %1, i32 0, i32 16, i32 1, i16 0, i32 16, <16 x i1> %cond)
   ret <16 x i32> %3
 }
+
+declare <16 x i8 addrspace(1)*> @llvm.genx.wrregioni.v16p1i8.i16.i1(<16 x i8 addrspace(1)*>, i8 addrspace(1)*, i32, i32, i32, i16, i32, i1)
+
+; CHECK-LABEL: @test_ptr_vector
+define <16 x i8 addrspace(1)*> @test_ptr_vector(i8 addrspace(1)* %p) {
+  ; CHECK: [[CAST:%[^ ]+]] = bitcast i8 addrspace(1)* %p to <1 x i8 addrspace(1)*>
+  ; CHECK: [[SPLAT:%[^ ]+]] = call <16 x i8 addrspace(1)*> @llvm.genx.rdregioni.v16p1i8.v1p1i8.i16(<1 x i8 addrspace(1)*> [[CAST]], i32 0, i32 16, i32 0, i16 0, i32 undef)
+  ; CHECK: ret <16 x i8 addrspace(1)*> [[SPLAT]]
+  %broadcast = call <16 x i8 addrspace(1)*> @llvm.genx.wrregioni.v16p1i8.i16.i1(<16 x i8 addrspace(1)*> undef, i8 addrspace(1)* %p, i32 0, i32 1, i32 0, i16 0, i32 undef, i1 true)
+  ret <16 x i8 addrspace(1)*> %broadcast
+}