Lower named barrier arrive VC intrinsic

vISA doesn't support divergent named barrier arrive instruction, so
lower it into raw send.

Author: vmustya

IGC/VectorCompiler/lib/GenXCodeGen/GenXLowering.cpp

@@ -260,6 +260,7 @@ class GenXLowering : public FunctionPass {
   bool lowerStackRestore(CallInst *CI);
   bool lowerHardwareThreadID(CallInst *CI);
   bool lowerLogicalThreadID(CallInst *CI);
+  bool lowerNamedBarrierArrive(CallInst *CI);
 
   Value *swapLowHighHalves(IRBuilder<> &Builder, Value *Arg) const;
   bool lowerByteSwap(CallInst *CI);
@@ -2170,6 +2171,8 @@ bool GenXLowering::processInst(Instruction *Inst) {
       return lowerHardwareThreadID(CI);
     case vc::InternalIntrinsic::logical_thread_id:
       return lowerLogicalThreadID(CI);
+    case GenXIntrinsic::genx_nbarrier_arrive:
+      return lowerNamedBarrierArrive(CI);
     }
     return false;
   }
@@ -4778,6 +4781,59 @@ bool GenXLowering::lowerLogicalThreadID(CallInst *CI) {
   return true;
 }
 
+bool GenXLowering::lowerNamedBarrierArrive(CallInst *CI) {
+  IGC_ASSERT(vc::getAnyIntrinsicID(CI) == GenXIntrinsic::genx_nbarrier_arrive);
+  if (!ST->hasNBarrier()) {
+    CI->getContext().emitError(CI, "Named barriers are not suppported by " +
+                                       ST->getCPU());
+    return false;
+  }
+
+  Module *M = CI->getModule();
+  IRBuilder<> Builder(CI);
+
+  const unsigned Width = ST->getGRFByteSize() / DWordBytes;
+  auto *Int32Ty = Builder.getInt32Ty();
+  auto *PayloadTy = IGCLLVM::FixedVectorType::get(Int32Ty, Width);
+  auto *UndefV = UndefValue::get(PayloadTy);
+
+  // Prepare named barrier message payload as follows:
+  //   payload[2][31:24]: number of consumers
+  //   payload[2][23:16]: number of producers
+  //   payload[2][15:14]: thread role
+  //   payload[2][4:0]: barrier id
+  auto *BarrierId = Builder.CreateZExt(CI->getArgOperand(0), Int32Ty);
+  auto *Role = Builder.CreateZExt(CI->getArgOperand(1), Int32Ty);
+  auto *NumProducers = Builder.CreateZExt(CI->getArgOperand(2), Int32Ty);
+  auto *NumConsumers = Builder.CreateZExt(CI->getArgOperand(3), Int32Ty);
+
+  auto *Payload = Builder.CreateAdd(BarrierId, Builder.CreateShl(Role, 14));
+  Payload = Builder.CreateAdd(Payload, Builder.CreateShl(NumProducers, 16));
+  Payload = Builder.CreateAdd(Payload, Builder.CreateShl(NumConsumers, 24));
+
+  Payload = Builder.CreateInsertElement(UndefV, Payload, 2);
+
+  SmallVector<Value *, 8> Args = {
+      Builder.getInt8(0),           // modifier (none)
+      Builder.getInt8(0),           // log2(exec size)
+      Builder.getTrue(),            // predicate
+      Builder.getInt8(1),           // number of source registers
+      Builder.getInt8(3),           // Gateway
+      Builder.getInt32(0),          // extened message descriptor
+      Builder.getInt32(0x02000004), // message descriptor: barrier
+      Payload,
+  };
+
+  auto *SendFunc =
+      vc::getAnyDeclaration(M, GenXIntrinsic::genx_raw_send2_noresult,
+                            {Builder.getInt1Ty(), PayloadTy});
+
+  Builder.CreateCall(SendFunc, Args);
+  ToErase.push_back(CI);
+
+  return true;
+}
+
 template <typename BuilderOp>
 bool GenXLowering::lowerReduction(CallInst *CI, Value *Src, Value *Start,
                                   BuilderOp Builder) {

IGC/VectorCompiler/test/Lowering/nbarrier_arrive.ll

@@ -0,0 +1,22 @@
+;=========================== begin_copyright_notice ============================
+;
+; Copyright (C) 2024 Intel Corporation
+;
+; SPDX-License-Identifier: MIT
+;
+;============================ end_copyright_notice =============================
+
+; RUN: %opt %use_old_pass_manager% -GenXLowering -march=genx64 -mcpu=XeHPC -mtriple=spir64-unknown-unknown -S < %s | FileCheck %s
+
+; RUN: not %opt %use_old_pass_manager% -GenXLowering -march=genx64 -mcpu=XeLP -mtriple=spir64-unknown-unknown -S < %s 2>&1 | FileCheck %s --check-prefix=CHECK-NO-NBARRIER
+
+declare void @llvm.genx.nbarrier.arrive(i8, i8, i8, i8)
+
+define spir_func void @test() {
+; CHECK: call void @llvm.genx.raw.send2.noresult.i1.v16i32(i8 0, i8 0, i1 true, i8 1, i8 3, i32 0, i32 33554436, <16 x i32> <i32 undef, i32 undef, i32 1075838988, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>)
+
+; CHECK-NO-NBARRIER: Named barriers are not suppported by XeLP
+
+  tail call void @llvm.genx.nbarrier.arrive(i8 12, i8 0, i8 32, i8 64)
+  ret void
+}