Minor refactoring and cleanup

* refactoring: intrinsic classes like `RTWriteIntrinsic` cleaned up
  and updated
* refactoring: intrinsic classes used instead of intrinsic ids, e.g. in checks
* obsolete code removed
* typo fixed: RTWritIntrinsic -> RTWriteIntrinsic

Author: MaciejKalinski

IGC/Compiler/CISACodeGen/CISABuilder.cpp

@@ -2271,7 +2271,6 @@ namespace IGC
         VISA_EMask_Ctrl emask = ConvertMaskToVisaType(m_encoderState.m_mask, m_encoderState.m_noMask);
         VISA_Exec_Size execSize = visaExecSize(m_encoderState.m_simdSize);
         VISA_PredOpnd* predOpnd = GetFlagOperand(m_encoderState.m_flag);
-        VISA_StateOpndHandle* surfOpnd = GetVISASurfaceOpnd(ESURFACE_NORMAL, bindingTableIndex);
 
         vISA_RT_CONTROLS cntrls;
         uint8_t numMsgSpecificOpnds = 0;
@@ -2354,35 +2353,37 @@ namespace IGC
         //vISA will decide whether to use it or not.
         VISA_RawOpnd* r1RegOpnd = GetRawSource(r1Reg);
 
-
-        if (CPSCounter)
-        {
-            V(vKernel->AppendVISA3dRTWriteCPS(
-                predOpnd,
-                emask,
-                execSize,
-                RTIndexOpnd,
-                cntrls,
-                surfOpnd,
-                r1RegOpnd,
-                sampleIndexOpnd,
-                cpsCounterOpnd,
-                numMsgSpecificOpnds,
-                srcOpnd));
-        }
-        else
         {
-            V(vKernel->AppendVISA3dRTWrite(
-                predOpnd,
-                emask,
-                execSize,
-                RTIndexOpnd,
-                cntrls,
-                surfOpnd,
-                r1RegOpnd,
-                sampleIndexOpnd,
-                numMsgSpecificOpnds,
-                srcOpnd));
+            VISA_StateOpndHandle* surfOpnd = GetVISASurfaceOpnd(ESURFACE_NORMAL, bindingTableIndex);
+            if (CPSCounter)
+            {
+                V(vKernel->AppendVISA3dRTWriteCPS(
+                    predOpnd,
+                    emask,
+                    execSize,
+                    RTIndexOpnd,
+                    cntrls,
+                    surfOpnd,
+                    r1RegOpnd,
+                    sampleIndexOpnd,
+                    cpsCounterOpnd,
+                    numMsgSpecificOpnds,
+                    srcOpnd));
+            }
+            else
+            {
+                V(vKernel->AppendVISA3dRTWrite(
+                    predOpnd,
+                    emask,
+                    execSize,
+                    RTIndexOpnd,
+                    cntrls,
+                    surfOpnd,
+                    r1RegOpnd,
+                    sampleIndexOpnd,
+                    numMsgSpecificOpnds,
+                    srcOpnd));
+            }
         }
     }
 

IGC/Compiler/CISACodeGen/CShader.cpp

@@ -205,33 +205,6 @@ void CShader::EOTURBWrite()
     encoder.Push();
 }
 
-void CShader::EOTRenderTarget(CVariable* r1, bool isPerCoarse)
-{
-    CVariable* src[4] = { nullptr, nullptr, nullptr, nullptr };
-    bool isUndefined[4] = { true, true, true, true };
-    CVariable* const nullSurfaceBti = ImmToVariable(m_pBtiLayout->GetNullSurfaceIdx(), ISA_TYPE_D);
-    CVariable* const blendStateIndex = ImmToVariable(0, ISA_TYPE_D);
-    SetBindingTableEntryCountAndBitmap(true, BUFFER_TYPE_UNKNOWN, 0, m_pBtiLayout->GetNullSurfaceIdx());
-    encoder.RenderTargetWrite(
-        src,
-        isUndefined,
-        true,  // lastRenderTarget,
-        true,  // Null RT
-        false, // perSample,
-        isPerCoarse, // coarseMode,
-        false, // isHeaderMaskFromCe0,
-        nullSurfaceBti,
-        blendStateIndex,
-        nullptr, // source0Alpha,
-        nullptr, // oMaskOpnd,
-        nullptr, // outputDepthOpnd,
-        nullptr, // stencilOpnd,
-        nullptr, // cpscounter,
-        nullptr, // sampleIndex,
-        r1);
-    encoder.Push();
-}
-
 // Creates a URB Fence message.
 // If return value is not a nullptr, the returned variable is a send message
 // writeback variable that must be read in order to wait for URB Fence
@@ -283,6 +256,35 @@ void CShader::EOTGateway(CVariable* payload)
     encoder.Push();
 }
 
+
+void CShader::EOTRenderTarget(CVariable* r1,
+    bool isPerCoarse)
+{
+    CVariable* src[4] = { nullptr, nullptr, nullptr, nullptr };
+    bool isUndefined[4] = { true, true, true, true };
+    CVariable* const nullSurfaceBti = ImmToVariable(m_pBtiLayout->GetNullSurfaceIdx(), ISA_TYPE_D);
+    CVariable* const blendStateIndex = ImmToVariable(0, ISA_TYPE_D);
+    SetBindingTableEntryCountAndBitmap(true, BUFFER_TYPE_UNKNOWN, 0, m_pBtiLayout->GetNullSurfaceIdx());
+    encoder.RenderTargetWrite(
+        src,
+        isUndefined,
+        true,  // lastRenderTarget,
+        true,  // Null RT
+        false, // perSample,
+        isPerCoarse, // coarseMode,
+        false, // isHeaderMaskFromCe0,
+        nullSurfaceBti,
+        blendStateIndex,
+        nullptr, // source0Alpha,
+        nullptr, // oMaskOpnd,
+        nullptr, // outputDepthOpnd,
+        nullptr, // stencilOpnd,
+        nullptr, // cpscounter,
+        nullptr, // sampleIndex,
+        r1);
+    encoder.Push();
+}
+
 void CShader::AddEpilogue(llvm::ReturnInst* ret)
 {
     encoder.EOT();

IGC/Compiler/CISACodeGen/CoalescingEngine.cpp

@@ -176,9 +176,8 @@ namespace IGC
 
                 if (GenIntrinsicInst * intrinsic = llvm::dyn_cast<llvm::GenIntrinsicInst>(DefMI))
                 {
-                    GenISAIntrinsic::ID IID = intrinsic->getIntrinsicID();
                     if ((isURBWriteIntrinsic(intrinsic) && !(IGC_IS_FLAG_ENABLED(DisablePayloadCoalescing_URB))) ||
-                        (IID == GenISAIntrinsic::GenISA_RTWrite && !(IGC_IS_FLAG_ENABLED(DisablePayloadCoalescing_RT))))
+                        (llvm::isa<llvm::RTWriteIntrinsic>(intrinsic) && !(IGC_IS_FLAG_ENABLED(DisablePayloadCoalescing_RT))))
                     {
                         ProcessTuple(DefMI);
                     }
@@ -450,15 +449,15 @@ namespace IGC
         if (ccTuple->HasNonHomogeneousElements())
         {
             // Finding a supremum instruction for a homogeneous part is implemented
-            // only for render target write instructions (RTWritIntrinsic).
+            // only for render target write instructions (RTWriteIntrinsic).
             // An only other possible combination for non-homogeneous instructions comprises
-            // RTWritIntrinsic and RTDualBlendSourceIntrinsic.
+            // RTWriteIntrinsic and RTDualBlendSourceIntrinsic.
             // In some cases there is an opportunity to coalesce their payloads but there exists
             // a danger that they are compiled in different SIMD modes so there is a safe assumption
             // that they cannot be coalesced.
-            // A comparison of the payload of RTWritIntrinsic and RTDualBlendSourceIntrinsic:
+            // A comparison of the payload of RTWriteIntrinsic and RTDualBlendSourceIntrinsic:
             // +----------------------------+----------------------------+
-            // | RTWritIntrinsic            | RTDualBlendSourceIntrinsic |
+            // | RTWriteIntrinsic            | RTDualBlendSourceIntrinsic |
             // +----------------------------+----------------------------+
             // | src0 Alpha (optional)      | src0 Alpha (unavailable)*  |
             // +----------------------------+----------------------------+
@@ -488,8 +487,8 @@ namespace IGC
             // * RTDualBlendSourceIntrinsic doesn't have such an argument but it is defined in its payload.
             if (offsetDiff == 0 &&
                 ccTuple->GetNumElements() == numOperands &&
-                llvm::isa<llvm::RTWritIntrinsic>(ccTuple->GetRoot()) &&
-                llvm::isa<llvm::RTWritIntrinsic>(tupleGeneratingInstruction))
+                llvm::isa<llvm::RTWriteIntrinsic>(ccTuple->GetRoot()) &&
+                llvm::isa<llvm::RTWriteIntrinsic>(tupleGeneratingInstruction))
             {
                 if (m_PayloadMapping.HasNonHomogeneousPayloadElements(tupleGeneratingInstruction))
                 {
@@ -1408,11 +1407,10 @@ namespace IGC
 
     bool CoalescingEngine::MatchSingleInstruction(llvm::GenIntrinsicInst* inst)
     {
-        GenISAIntrinsic::ID IID = inst->getIntrinsicID();
         if (isSampleInstruction(inst) ||
             isLdInstruction(inst) ||
             isURBWriteIntrinsic(inst) ||
-            IID == GenISAIntrinsic::GenISA_RTWrite)
+            llvm::isa<llvm::RTWriteIntrinsic>(inst))
         {
             uint numOperands = inst->getNumOperands();
             for (uint i = 0; i < numOperands; i++)