Introduce surface commoning

.

Author: KorovinVlad

IGC/VectorCompiler/lib/GenXCodeGen/GenXCategory.cpp

@@ -201,6 +201,7 @@ namespace {
   private:
     using ConvListT = std::array<llvm::Instruction *, vc::numRegCategories()>;
 
+    bool commonUpSurface(BasicBlock *BB);
     bool processFunction(Function *F);
     bool fixCircularPhis(Function *F);
     bool processValue(Value *V);
@@ -505,6 +506,50 @@ static bool commonUpPredicate(BasicBlock *BB) {
   return Changed;
 }
 
+/***********************************************************************
+ * isToSurfaceConversion : returns true if the input instruction is a
+ * surface conversion intrinsic.
+ */
+static bool isToSurfaceConversion(Instruction *I,
+                                  const GenXLiveness *Liveness) {
+  if (IntrinsicInst *IC = dyn_cast<IntrinsicInst>(I)) {
+    unsigned IntrinsicID = vc::getAnyIntrinsicID(IC);
+    if (IntrinsicID != GenXIntrinsic::genx_convert)
+      return false;
+    if (auto LR = Liveness->getLiveRangeOrNull(I)) {
+      auto Cat = LR->getCategory();
+      if (Cat == vc::RegCategory::Surface)
+        return true;
+    }
+  }
+  return false;
+}
+
+/***********************************************************************
+ * commonUpSurface : perform surface commoning to reduce number of
+ * instructions to stop the surface conversion falling outside of the
+ * register into which it points to avoid going out of spec (256). The
+ * logic is applied within a basic block to avoid dramatic live ranges
+ * increase.
+ */
+bool GenXCategory::commonUpSurface(BasicBlock *BB) {
+  bool Modified = false;
+  // Maps the original value to after-conversion value.
+  SmallDenseMap<Value *, Value *> ConvMap;
+  for (auto bi = BB->begin(), be = BB->end(); bi != be; ++bi) {
+    Instruction *I = &*bi;
+    if (!isToSurfaceConversion(I, Liveness))
+      continue;
+    IGC_ASSERT(I->hasOneUse());
+    if (!ConvMap.insert({I->getOperand(0), I}).second) {
+      Modified = true;
+      I->replaceAllUsesWith(ConvMap[I->getOperand(0)]);
+      ToErase.push_back(I);
+    }
+  }
+  return Modified;
+}
+
 /***********************************************************************
  * processFunction : run the category conversion pass for this Function
  *
@@ -538,6 +583,8 @@ bool GenXCategory::processFunction(Function *F)
 
     // This commons up constpred calls just loaded.
     Modified |= commonUpPredicate(BB);
+    // This commons up to-surface conversion calls.
+    Modified |= commonUpSurface(BB);
 
     // Erase instructions (and their live ranges) as requested by processValue.
     for (unsigned i = 0, e = ToErase.size(); i != e; ++i) {

IGC/VectorCompiler/test/GenXCategory/surface-commoning.ll

@@ -0,0 +1,62 @@
+;=========================== begin_copyright_notice ============================
+;
+; Copyright (C) 2023 Intel Corporation
+;
+; SPDX-License-Identifier: MIT
+;
+;============================ end_copyright_notice =============================
+
+; RUN: opt %use_old_pass_manager% -GenXModule -GenXNumberingWrapper -GenXLiveRangesWrapper -GenXCategoryWrapper \
+; RUN: -march=genx64 -mtriple=spir64-unknown-unknown  -mcpu=Gen9 -S < %s | FileCheck %s
+
+; Function Attrs: nofree nounwind readonly
+declare <32 x i32> @llvm.genx.oword.ld.unaligned.v32i32(i32, i32, i32) #1
+
+; Function Attrs: nounwind
+declare void @llvm.genx.oword.st.v32i32(i32, i32, <32 x i32>) #2
+
+define dllexport void @kernel(i32 %offset, i64 %impl.arg.private.base) #0 {
+entry:
+  ; CHECK: call i32 @llvm.genx.convert.i32(i32 2)
+  %ld1 = tail call <32 x i32> @llvm.genx.oword.ld.unaligned.v32i32(i32 0, i32 2, i32 %offset)
+  ; CHECK: call i32 @llvm.genx.convert.i32(i32 3)
+  %ld3 = tail call <32 x i32> @llvm.genx.oword.ld.unaligned.v32i32(i32 0, i32 3, i32 %offset)
+  ; CHECK-NOT: call i32 @llvm.genx.convert.i32(i32 3)
+  call void @llvm.genx.oword.st.v32i32(i32 3, i32 0, <32 x i32> %ld1)
+  ; CHECK-NOT: call i32 @llvm.genx.convert.i32(i32 2)
+  call void @llvm.genx.oword.st.v32i32(i32 2, i32 0, <32 x i32> %ld3)
+  br label %BB
+BB:
+  ; CHECK: BB
+  ; CHECK: call i32 @llvm.genx.convert.i32(i32 2)
+  %ld7 = tail call <32 x i32> @llvm.genx.oword.ld.unaligned.v32i32(i32 0, i32 2, i32 %offset)
+  ; CHECK: call i32 @llvm.genx.convert.i32(i32 3)
+  %ld9 = tail call <32 x i32> @llvm.genx.oword.ld.unaligned.v32i32(i32 0, i32 3, i32 %offset)
+  ; CHECK-NOT: call i32 @llvm.genx.convert.i32(i32 3)
+  call void @llvm.genx.oword.st.v32i32(i32 3, i32 128, <32 x i32> %ld7)
+  ; CHECK-NOT: call i32 @llvm.genx.convert.i32(i32 2)
+  call void @llvm.genx.oword.st.v32i32(i32 2, i32 128, <32 x i32> %ld9)
+  ret void
+}
+
+attributes #0 = { "CMGenxMain" }
+attributes #1 = { nofree nounwind readonly }
+attributes #2 = { nounwind }
+
+!genx.kernels = !{!6}
+!genx.kernel.internal = !{!11}
+
+!0 = !{i32 2, i32 2}
+!1 = !{i32 0, i32 0}
+!2 = !{i32 1, i32 2}
+!3 = !{i32 2, i32 0}
+!4 = !{}
+!5 = !{i16 6, i16 14}
+!6 = !{void (i32, i64)* @kernel, !"kernel", !7, i32 0, !8, !9, !10, i32 0}
+!7 = !{i32 0, i32 96}
+!8 = !{i32 72, i32 64}
+!9 = !{i32 0}
+!10 = !{!""}
+!11 = !{void (i32, i64)* @kernel, !1, !12, !4, !13}
+!12 = !{i32 0, i32 1}
+!13 = !{i32 -1, i32 1}