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pkwasnie-inteligcbot
pkwasnie-intel
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indirect access detection - load/store GenISA intrinsics
support * Adds support of load/store GenISA intrinsics to ScalarArgAsPointerAnalysis pass. * Adds missing atomics to opCode.h.
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7 files changed

+118
-6
lines changed

7 files changed

+118
-6
lines changed

‎IGC/AdaptorOCL/ocl_igc_shared/indirect_access_detection/version.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -13,4 +13,4 @@ SPDX-License-Identifier: MIT
1313

1414
#pragma once
1515

16-
const uint32_t INDIRECT_ACCESS_DETECTION_VERSION = 1;
16+
const uint32_t INDIRECT_ACCESS_DETECTION_VERSION = 2;

‎IGC/Compiler/CISACodeGen/helper.cpp

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1755,6 +1755,7 @@ namespace IGC
17551755
case GenISAIntrinsic::GenISA_LSCStore:
17561756
case GenISAIntrinsic::GenISA_LSCStoreBlock:
17571757
case GenISAIntrinsic::GenISA_simdBlockWrite:
1758+
case GenISAIntrinsic::GenISA_LSC2DBlockWrite:
17581759
return true;
17591760
default:
17601761
break;

‎IGC/Compiler/CISACodeGen/opCode.h

Lines changed: 10 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -164,11 +164,21 @@ DECLARE_OPCODE(GenISA_firstbitHi, GenISAIntrinsic, llvm_fbh, false, false, false
164164
DECLARE_OPCODE(GenISA_firstbitLo, GenISAIntrinsic, llvm_fbl, false, false, false, false, true, false, false)
165165
DECLARE_OPCODE(GenISA_firstbitShi, GenISAIntrinsic, llvm_fbh_shi, false, false, false, false, true, false, false)
166166
DECLARE_OPCODE(GenISA_intatomicraw, GenISAIntrinsic, llvm_int_atomic_raw, false, false, false, false, false, true, false)
167+
DECLARE_OPCODE(GenISA_floatatomicraw, GenISAIntrinsic, llvm_float_atomic_raw, false, false, false, false, false, true, false)
168+
DECLARE_OPCODE(GenISA_intatomicrawA64, GenISAIntrinsic, llvm_int_atomic_raw_A64, false, false, false, false, false, true, false)
169+
DECLARE_OPCODE(GenISA_floatatomicrawA64, GenISAIntrinsic, llvm_float_atomic_raw_A64, false, false, false, false, false, true, false)
167170
DECLARE_OPCODE(GenISA_dwordatomicstructured, GenISAIntrinsic, llvm_dword_atomic_structured, false, false, false, false, false, true, false)
171+
DECLARE_OPCODE(GenISA_floatatomicstructured, GenISAIntrinsic, llvm_float_atomic_structured, false, false, false, false, false, true, false)
168172
DECLARE_OPCODE(GenISA_intatomictyped, GenISAIntrinsic, llvm_int_atomic_typed, false, false, false, false, false, true, false)
173+
DECLARE_OPCODE(GenISA_floatatomictyped, GenISAIntrinsic, llvm_float_atomic_typed, false, false, false, false, false, true, false)
169174
DECLARE_OPCODE(GenISA_icmpxchgatomicraw, GenISAIntrinsic, llvm_icmpxchg_atomic_raw, false, false, false, false, false, true, false)
175+
DECLARE_OPCODE(GenISA_fcmpxchgatomicraw, GenISAIntrinsic, llvm_fcmpxchg_atomic_raw, false, false, false, false, false, true, false)
176+
DECLARE_OPCODE(GenISA_icmpxchgatomicrawA64, GenISAIntrinsic, llvm_icmpxchg_atomic_raw_A64, false, false, false, false, false, true, false)
177+
DECLARE_OPCODE(GenISA_fcmpxchgatomicrawA64, GenISAIntrinsic, llvm_fcmpxchg_atomic_raw_A64, false, false, false, false, false, true, false)
170178
DECLARE_OPCODE(GenISA_cmpxchgatomicstructured, GenISAIntrinsic, llvm_cmpxchg_atomic_structured, false, false, false, false, false, true, false)
179+
DECLARE_OPCODE(GenISA_fcmpxchgatomicstructured, GenISAIntrinsic, llvm_fcmpxchg_atomic_structured, false, false, false, false, false, true, false)
171180
DECLARE_OPCODE(GenISA_icmpxchgatomictyped, GenISAIntrinsic, llvm_icmpxchg_atomic_typed, false, false, false, false, false, true, false)
181+
DECLARE_OPCODE(GenISA_fcmpxchgatomictyped, GenISAIntrinsic, llvm_fcmpxchg_atomic_typed, false, false, false, false, false, true, false)
172182
DECLARE_OPCODE(GenISA_atomiccounterinc, GenISAIntrinsic, llvm_atomic_counter_inc, false, false, false, false, false, true, false)
173183
DECLARE_OPCODE(GenISA_atomiccounterpredec, GenISAIntrinsic, llvm_atomic_counter_predec, false, false, false, false, false, true, false)
174184

‎IGC/Compiler/Optimizer/OpenCLPasses/ScalarArgAsPointer/ScalarArgAsPointer.cpp

Lines changed: 43 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -101,6 +101,33 @@ void ScalarArgAsPointerAnalysis::visitLoadInst(llvm::LoadInst& I)
101101
analyzePointer(I.getPointerOperand());
102102
}
103103

104+
void ScalarArgAsPointerAnalysis::visitCallInst(CallInst& CI)
105+
{
106+
auto I = dyn_cast<GenIntrinsicInst>(&CI);
107+
if (!I)
108+
return;
109+
110+
GenISAIntrinsic::ID const id = I->getIntrinsicID();
111+
112+
if (id == GenISAIntrinsic::GenISA_LSC2DBlockRead ||
113+
id == GenISAIntrinsic::GenISA_LSC2DBlockWrite)
114+
{
115+
return analyzeValue(I->getOperand(0));
116+
}
117+
118+
if (IsStatelessMemLoadIntrinsic(id) ||
119+
IsStatelessMemStoreIntrinsic(id) ||
120+
IsStatelessMemAtomicIntrinsic(*I, id))
121+
{
122+
Value* V = GetBufferOperand(I);
123+
124+
if (!V || !isa<PointerType>(V->getType()))
125+
return;
126+
127+
return analyzePointer(V);
128+
}
129+
}
130+
104131
void ScalarArgAsPointerAnalysis::analyzePointer(llvm::Value* V)
105132
{
106133
auto* type = dyn_cast<PointerType>(V->getType());
@@ -110,12 +137,23 @@ void ScalarArgAsPointerAnalysis::analyzePointer(llvm::Value* V)
110137
if (type->getAddressSpace() != ADDRESS_SPACE_GLOBAL && type->getAddressSpace() != ADDRESS_SPACE_GENERIC)
111138
return;
112139

113-
// If scalar is going to be used as pointer, it has to be an instruction, like casting.
114-
auto* inst = dyn_cast<Instruction>(V);
115-
if (!inst)
116-
return;
140+
analyzeValue(V);
141+
}
142+
143+
void ScalarArgAsPointerAnalysis::analyzeValue(llvm::Value* V)
144+
{
145+
std::shared_ptr<ScalarArgAsPointerAnalysis::ArgSet> args;
146+
147+
if (auto* I = dyn_cast<Instruction>(V))
148+
{
149+
args = findArgs(I);
150+
}
151+
else
152+
{
153+
args = analyzeOperand(V);
154+
}
117155

118-
if (auto args = findArgs(inst))
156+
if (args)
119157
{
120158
LLVM_DEBUG(
121159
for (auto a : *args)

‎IGC/Compiler/Optimizer/OpenCLPasses/ScalarArgAsPointer/ScalarArgAsPointer.hpp

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -68,6 +68,7 @@ namespace IGC
6868

6969
void visitStoreInst(llvm::StoreInst& I);
7070
void visitLoadInst(llvm::LoadInst& I);
71+
void visitCallInst(llvm::CallInst& I);
7172

7273
private:
7374

@@ -83,6 +84,8 @@ namespace IGC
8384
/// @param V destination pointer.
8485
void analyzePointer(llvm::Value* V);
8586

87+
void analyzeValue(llvm::Value* V);
88+
8689
/// @brief Returns a set of matching kernel arguments. Returns null if load/store:
8790
/// (1) is indirect, or
8891
/// (2) uses pointer kernel argument

‎IGC/Compiler/tests/ScalarArgAsPointer/LSC2DBlock.ll

Lines changed: 31 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,31 @@
1+
;=========================== begin_copyright_notice ============================
2+
;
3+
; Copyright (C) 2024 Intel Corporation
4+
;
5+
; SPDX-License-Identifier: MIT
6+
;
7+
;============================ end_copyright_notice =============================
8+
9+
; RUN: igc_opt --igc-scalar-arg-as-pointer-analysis --serialize-igc-metadata -S %s | FileCheck %s
10+
;
11+
; CHECK: !{!"m_OpenCLArgScalarAsPointersSet{{[[][0-9][]]}}", i32 0}
12+
; CHECK: !{!"m_OpenCLArgScalarAsPointersSet{{[[][0-9][]]}}", i32 1}
13+
; CHECK-NOT: !{!"m_OpenCLArgScalarAsPointersSet{{[[][0-9][]]}}", i32 2}
14+
15+
define spir_kernel void @test(i64 %a, i64 %b, i64 %c) #0 {
16+
entry:
17+
%0 = call <8 x i32> @llvm.genx.GenISA.LSC2DBlockRead.v8i32(i64 %a, i32 8191, i32 7, i32 8191, i32 0, i32 0, i32 32, i32 16, i32 8, i32 1, i1 false, i1 false)
18+
call void @llvm.genx.GenISA.LSC2DBlockWrite.v8i32(i64 %b, i32 8191, i32 7, i32 8191, i32 0, i32 0, i32 32, i32 16, i32 8, i32 1, i1 false, i1 false, <8 x i32> %0)
19+
ret void
20+
}
21+
22+
declare <8 x i32> @llvm.genx.GenISA.LSC2DBlockRead.v8i32(i64, i32, i32, i32, i32, i32, i32, i32, i32, i32, i1, i1) #1
23+
declare void @llvm.genx.GenISA.LSC2DBlockWrite.v8i32(i64, i32, i32, i32, i32, i32, i32, i32, i32, i32, i1, i1, <8 x i32>) #1
24+
25+
attributes #1 = { nounwind }
26+
27+
!igc.functions = !{!0}
28+
29+
!0 = !{void (i64, i64, i64)* @test, !1}
30+
!1 = !{!2}
31+
!2 = !{!"function_type", i32 0}

‎IGC/Compiler/tests/ScalarArgAsPointer/floatatomic.ll

Lines changed: 29 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,29 @@
1+
;=========================== begin_copyright_notice ============================
2+
;
3+
; Copyright (C) 2024 Intel Corporation
4+
;
5+
; SPDX-License-Identifier: MIT
6+
;
7+
;============================ end_copyright_notice =============================
8+
9+
; RUN: igc_opt --igc-scalar-arg-as-pointer-analysis --serialize-igc-metadata -S %s | FileCheck %s
10+
;
11+
; CHECK: !{!"m_OpenCLArgScalarAsPointersSet{{[[][0-9][]]}}", i32 0}
12+
; CHECK-NOT: !{!"m_OpenCLArgScalarAsPointersSet{{[[][0-9][]]}}", i32 1}
13+
14+
define spir_kernel void @test(i64 %a, double %b) #0 {
15+
entry:
16+
%0 = inttoptr i64 %a to double addrspace(1)*
17+
%1 = call double @llvm.genx.GenISA.floatatomicrawA64.f64.p1f64.p1f64(double addrspace(1)* %0, double addrspace(1)* %0, double %b, i32 21)
18+
ret void
19+
}
20+
21+
declare double @llvm.genx.GenISA.floatatomicrawA64.f64.p1f64.p1f64(double addrspace(1)*, double addrspace(1)*, double, i32) #1
22+
23+
attributes #1 = { nounwind }
24+
25+
!igc.functions = !{!0}
26+
27+
!0 = !{void (i64, double)* @test, !1}
28+
!1 = !{!2}
29+
!2 = !{!"function_type", i32 0}

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