Insert HDC fence before EOT when sparse aliased resources may be present.

Change-Id: Ia177317ed91e0058e16d227d7f2a1019f9eeb74d

Author: krystian-andrzejewski

IGC/Compiler/CISACodeGen/CISABuilder.cpp

@@ -3812,7 +3812,13 @@ namespace IGC
         SaveOption(vISA_clearScratchWritesBeforeEOT, true);
     }
 
-    if (context->type == ShaderType::PIXEL_SHADER)
+    bool clearHDCWritesBeforeEOT = m_program->m_DriverInfo->UsesSparseAliasedResidency() &&
+        context->platform.WaInsertHDCFenceBeforeEOTWhenSparseAliasedResources();
+    clearHDCWritesBeforeEOT |= context->type == ShaderType::PIXEL_SHADER &&
+        context->platform.NeedsHDCFenceBeforeEOTInPixelShader();
+    clearHDCWritesBeforeEOT |= IGC_IS_FLAG_ENABLED(ForceMemoryFenceBeforeEOT);
+
+    if (clearHDCWritesBeforeEOT)
     {
         SaveOption(vISA_clearHDCWritesBeforeEOT, true);
     }

IGC/Compiler/CISACodeGen/DriverInfo.hpp

@@ -80,6 +80,9 @@ namespace IGC
         /// The driver uses typed or untyped constant buffers (for ld_raw vs sampler)
         virtual bool UsesTypedConstantBuffersGPGPU() const { return true; }
 
+        /// The driver uses sparse aliased residency
+        virtual bool UsesSparseAliasedResidency() const { return false; }
+
         /// The driver doesn't clear the vertex header so it needs to be done in the compiler
         virtual bool NeedClearVertexHeader() const { return false; }
 

IGC/Compiler/CISACodeGen/Platform.hpp

@@ -373,6 +373,10 @@ namespace IGC
         return true;
     }
 
+    bool NeedsHDCFenceBeforeEOTInPixelShader() const
+    {
+        return false;
+    }
     // ***** Below go accessor methods for testing WA data from WA_TABLE *****
 
     bool WaDoNotPushConstantsForAllPulledGSTopologies() const
@@ -475,6 +479,11 @@ namespace IGC
 
     }
 
+    bool WaInsertHDCFenceBeforeEOTWhenSparseAliasedResources() const
+    {
+        return IGFX_GEN11_CORE >= m_platformInfo.eRenderCoreFamily;
+    }
+
         const SCompilerHwCaps& GetCaps() { return m_caps; }
     };
 

IGC/common/igc_flags.def

@@ -201,6 +201,7 @@ DECLARE_IGC_REGKEY(DWORD, RetryManagerFirstStateId,     0,     "For debugging pu
 DECLARE_IGC_REGKEY(bool, DisableSendSrcDstOverlapWA,    false, "Disable Send Source/destination overlap WA which is enabled for GEN10/GEN11 and whenever Wddm2Svm is set in WATable", false)
 DECLARE_IGC_REGKEY(debugString, DisablePassToggles,     0,     "Disable each IGC pass by setting the bit. HEXADECIMAL ONLY!. Ex: C0 is to disable pass 6 and pass 7.", false)
 DECLARE_IGC_REGKEY(bool, ForceStatelessForQueueT,       true,  "In OCL, force to use stateless memory to hold queue_t*. This is a legacy feature to be removed.", false)
+DECLARE_IGC_REGKEY(bool, ForceMemoryFenceBeforeEOT,     false,  "Forces inserting SLM or gloabal memory fence before EOT if shader writes to SLM or goblam memory respectively.", false)
 
 DECLARE_IGC_GROUP("Shader dumping")
 DECLARE_IGC_REGKEY(bool, EnableCosDump, false, "Enable cos dump", true)

visa/Optimizer.cpp

@@ -8058,7 +8058,7 @@ void genBucket(G4_INST *send, Bucket *bucket, RW rwType) {
     // ToDo: add fence only when the writes can reach EOT without a fence in between
     void Optimizer::insertFenceBeforeEOT()
     {
-        if (!builder.needFenceBeforeEOT() || !builder.getOption(vISA_clearHDCWritesBeforeEOT))
+        if (!builder.getOption(vISA_clearHDCWritesBeforeEOT))
         {
             return;
         }