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Add support for SPIRV MulExtended instructions in VC
Enable SPIRV UMulExtended and SMulExtended instructions
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‎IGC/VectorCompiler/lib/GenXOpts/CMTrans/GenXTranslateSPIRVBuiltins.cpp

Lines changed: 39 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
/*========================== begin_copyright_notice ============================
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3-
Copyright (C) 2021-2024 Intel Corporation
3+
Copyright (C) 2021-2025 Intel Corporation
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SPDX-License-Identifier: MIT
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@@ -69,6 +69,7 @@ class SPIRVExpander : public InstVisitor<SPIRVExpander, Value *> {
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ArrayRef<Value *> Args, bool AFN = false);
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Value *emitFDiv(IRBuilder<> &Builder, Value *L, Value *R, bool ARCP = false);
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Value *emitAddcSubb(IRBuilder<> &Builder, unsigned IID, CallInst &CI);
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Value *emitMulExtended(IRBuilder<> &Builder, unsigned IID, CallInst &CI);
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Value *emitDot(IRBuilder<> &Builder, unsigned IID, CallInst &CI);
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Module *M;
@@ -117,6 +118,7 @@ Value *SPIRVExpander::emitAddcSubb(IRBuilder<> &Builder, unsigned IID,
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if (ArgTy->getScalarType()->getPrimitiveSizeInBits() < 32) {
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vc::diagnose(CI.getFunction()->getContext(), "GenXTranslateSPIRV",
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"only 32/64-bit addc/subb supported", &CI);
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return nullptr;
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}
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auto *Instr = emitIntrinsic(Builder, IID, {ArgTy, ArgTy},
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{CI.getArgOperand(1), CI.getArgOperand(2)});
@@ -144,6 +146,34 @@ Value *SPIRVExpander::emitAddcSubb(IRBuilder<> &Builder, unsigned IID,
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Builder.CreateStore(ExtRes, ResPtr);
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return Builder.CreateStore(Carry, CarryPtr);
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}
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Value *SPIRVExpander::emitMulExtended(IRBuilder<> &Builder, unsigned IID,
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CallInst &CI) {
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auto *Res = CI.getArgOperand(0);
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auto *Ty = CI.getArgOperand(1)->getType();
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if (Ty->getScalarType()->getPrimitiveSizeInBits() != 32) {
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vc::diagnose(CI.getFunction()->getContext(), "GenXTranslateSPIRV",
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"only 32 MulExtended supported", &CI);
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return nullptr;
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}
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auto *Zero = Constant::getNullValue(Ty);
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auto *Instr = emitIntrinsic(Builder, IID, {Ty, Ty},
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{CI.getArgOperand(1), CI.getArgOperand(2), Zero});
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auto *Lo = Builder.CreateExtractValue(Instr, {0});
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auto *Hi = Builder.CreateExtractValue(Instr, {1});
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unsigned int AddrSpace = cast<PointerType>(Res->getType())->getAddressSpace();
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Res = Builder.CreateBitCast(Res, PointerType::get(Ty, AddrSpace));
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auto *LoPtr = Builder.CreateGEP(Ty, Res, Builder.getInt32(0));
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auto *HiPtr = Builder.CreateGEP(Ty, Res, Builder.getInt32(1));
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Builder.CreateStore(Lo, LoPtr);
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return Builder.CreateStore(Hi, HiPtr);
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}
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Value *SPIRVExpander::emitDot(IRBuilder<> &Builder, unsigned IID,
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CallInst &CI) {
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auto *Ty = CI.getType();
@@ -248,6 +278,14 @@ Value *SPIRVExpander::visitCallInst(CallInst &CI) {
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if (IID != Intrinsic::not_intrinsic)
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return emitAddcSubb(Builder, IID, CI);
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IID = StringSwitch<unsigned>(CalleeName)
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.StartsWith("UMulExtended", GenXIntrinsic::genx_uimad)
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.StartsWith("SMulExtended", GenXIntrinsic::genx_simad)
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.Default(Intrinsic::not_intrinsic);
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if (IID != Intrinsic::not_intrinsic)
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return emitMulExtended(Builder, IID, CI);
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251289
if (CalleeName.startswith("Dot")) {
252290
return emitDot(Builder, IID, CI);
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}

‎IGC/VectorCompiler/test/GenXTranslateSPIRVBuiltins/mulext.ll

Lines changed: 79 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,79 @@
1+
;=========================== begin_copyright_notice ============================
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;
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; Copyright (C) 2025 Intel Corporation
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;
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; SPDX-License-Identifier: MIT
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;
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;============================ end_copyright_notice =============================
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;
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; RUN: %opt_legacy_typed %use_old_pass_manager% -GenXTranslateSPIRVBuiltins \
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; RUN: -vc-spirv-builtins-bif-path=%VC_SPIRV_OCL_BIF% -march=genx64 \
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; RUN: -mtriple=spir64-unknown-unknown -mcpu=XeHPC -S < %s | FileCheck %s --check-prefixes=CHECK,CHECK-TYPED-PTRS
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; RUN: %opt_legacy_opaque %use_old_pass_manager% -GenXTranslateSPIRVBuiltins \
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; RUN: -vc-spirv-builtins-bif-path=%VC_SPIRV_OCL_BIF% -march=genx64 \
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; RUN: -mtriple=spir64-unknown-unknown -mcpu=XeHPC -S < %s | FileCheck %s --check-prefixes=CHECK,CHECK-OPAQUE-PTRS
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; RUN: %opt_new_pm_typed -passes=GenXTranslateSPIRVBuiltins \
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; RUN: -vc-spirv-builtins-bif-path=%VC_SPIRV_OCL_BIF% -march=genx64 \
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; RUN: -mtriple=spir64-unknown-unknown -mcpu=XeHPC -S < %s | FileCheck %s --check-prefixes=CHECK,CHECK-TYPED-PTRS
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; RUN: %opt_new_pm_opaque -passes=GenXTranslateSPIRVBuiltins \
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; RUN: -vc-spirv-builtins-bif-path=%VC_SPIRV_OCL_BIF% -march=genx64 \
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; RUN: -mtriple=spir64-unknown-unknown -mcpu=XeHPC -S < %s | FileCheck %s --check-prefixes=CHECK,CHECK-OPAQUE-PTRS
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; ------------------------------------------------
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; GenXTranslateSPIRVBuiltins
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; ------------------------------------------------
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; This test checks that GenXTranslateSPIRVBuiltins translates addc
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%struct_pair = type { <16 x i32>, <16 x i32> }
27+
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; CHECK: [[UIMAD:%[^ ]*]] = call { <16 x i32>, <16 x i32> } @llvm.genx.uimad.v16i32.v16i32(<16 x i32> {{.*}}, <16 x i32> {{.*}})
29+
; CHECK: [[LO:%[^ ]*]] = extractvalue { <16 x i32>, <16 x i32> } [[UIMAD]], 0
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; CHECK: [[HI:%[^ ]*]] = extractvalue { <16 x i32>, <16 x i32> } [[UIMAD]], 1
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; CHECK-TYPED-PTRS: [[PTR_CAST:%[^ ]*]] = bitcast %struct_pair addrspace(4)* {{.*}} to <16 x i32> addrspace(4)*
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; CHECK-TYPED-PTRS: [[PTR_LO:%[^ ]*]] = getelementptr <16 x i32>, <16 x i32> addrspace(4)* [[PTR_CAST]], i32 0
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; CHECK-TYPED-PTRS: [[PTR_HI:%[^ ]*]] = getelementptr <16 x i32>, <16 x i32> addrspace(4)* [[PTR_CAST]], i32 1
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; CHECK-TYPED-PTRS: store <16 x i32> [[LO]], <16 x i32> addrspace(4)* [[PTR_LO]], align 64
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; CHECK-TYPED-PTRS: store <16 x i32> [[HI]], <16 x i32> addrspace(4)* [[PTR_HI]], align 64
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; CHECK-OPAQUE-PTRS: [[PTR_LO:%[^ ]*]] = getelementptr <16 x i32>, ptr addrspace(4) {{.*}}, i32 0
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; CHECK-OPAQUE-PTRS: [[PTR_HI:%[^ ]*]] = getelementptr <16 x i32>, ptr addrspace(4) {{.*}}, i32 1
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; CHECK-OPAQUE-PTRS: store <16 x i32> [[LO]], ptr addrspace(4) [[PTR_LO]], align 64
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; CHECK-OPAQUE-PTRS: store <16 x i32> [[HI]], ptr addrspace(4) [[PTR_HI]], align 64
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; Function Attrs: nounwind
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define dllexport spir_kernel void @test_umul() #0 {
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entry:
44+
%alloca1 = alloca %struct_pair, align 64
45+
%alloca2 = addrspacecast %struct_pair* %alloca1 to %struct_pair addrspace(4)*
46+
%first = add <16 x i32> zeroinitializer, <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
47+
%second = add <16 x i32> zeroinitializer, <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
48+
call spir_func void @_Z20__spirv_UMulExtendedDv16_iS_(%struct_pair addrspace(4)* sret(%struct_pair) %alloca2, <16 x i32> %first, <16 x i32> %second)
49+
ret void
50+
}
51+
declare spir_func void @_Z20__spirv_UMulExtendedDv16_iS_(%struct_pair addrspace(4)* sret(%struct_pair), <16 x i32>, <16 x i32>)
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; CHECK: [[SIMAD:%[^ ]*]] = call { <16 x i32>, <16 x i32> } @llvm.genx.simad.v16i32.v16i32(<16 x i32> {{.*}}, <16 x i32> {{.*}})
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; CHECK: [[LO:%[^ ]*]] = extractvalue { <16 x i32>, <16 x i32> } [[SIMAD]], 0
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; CHECK: [[HI:%[^ ]*]] = extractvalue { <16 x i32>, <16 x i32> } [[SIMAD]], 1
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; CHECK-TYPED-PTRS: [[PTR_CAST:%[^ ]*]] = bitcast %struct_pair addrspace(4)* {{.*}} to <16 x i32> addrspace(4)*
57+
; CHECK-TYPED-PTRS: [[PTR_LO:%[^ ]*]] = getelementptr <16 x i32>, <16 x i32> addrspace(4)* [[PTR_CAST]], i32 0
58+
; CHECK-TYPED-PTRS: [[PTR_HI:%[^ ]*]] = getelementptr <16 x i32>, <16 x i32> addrspace(4)* [[PTR_CAST]], i32 1
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; CHECK-TYPED-PTRS: store <16 x i32> [[LO]], <16 x i32> addrspace(4)* [[PTR_LO]], align 64
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; CHECK-TYPED-PTRS: store <16 x i32> [[HI]], <16 x i32> addrspace(4)* [[PTR_HI]], align 64
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; CHECK-OPAQUE-PTRS: [[PTR_LO:%[^ ]*]] = getelementptr <16 x i32>, ptr addrspace(4) {{.*}}, i32 0
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; CHECK-OPAQUE-PTRS: [[PTR_HI:%[^ ]*]] = getelementptr <16 x i32>, ptr addrspace(4) {{.*}}, i32 1
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; CHECK-OPAQUE-PTRS: store <16 x i32> [[LO]], ptr addrspace(4) [[PTR_LO]], align 64
64+
; CHECK-OPAQUE-PTRS: store <16 x i32> [[HI]], ptr addrspace(4) [[PTR_HI]], align 64
65+
66+
; Function Attrs: nounwind
67+
define dllexport spir_kernel void @test_smul() #0 {
68+
entry:
69+
%alloca1 = alloca %struct_pair, align 64
70+
%alloca2 = addrspacecast %struct_pair* %alloca1 to %struct_pair addrspace(4)*
71+
%first = add <16 x i32> zeroinitializer, <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
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%second = add <16 x i32> zeroinitializer, <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
73+
call spir_func void @_Z20__spirv_SMulExtendedDv16_iS_(%struct_pair addrspace(4)* sret(%struct_pair) %alloca2, <16 x i32> %first, <16 x i32> %second)
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ret void
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}
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declare spir_func void @_Z20__spirv_SMulExtendedDv16_iS_(%struct_pair addrspace(4)* sret(%struct_pair), <16 x i32>, <16 x i32>)
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attributes #0 = { nounwind "CMGenxMain" "oclrt"="1" }
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