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[IGC Core] LSC 2D load splits: block loads
Coalescing block reads can improve performance significantly, as it decreases the number of block read instructions, decrease the address payload required by the block reads, etc. However, block reads coalescing is not always profitable, e.g., in the situation of high register pressure, more block reads can decrease live ranges. This is the first PR of the series of PRs that splits large block reads into smaller blocks. It provides an interface and a pass for splitting block loads (i.e., old style intrinsics) into smaller loads. The following PRs will extend the functionality of the pass to more general cases.
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‎IGC/Compiler/CISACodeGen/CMakeLists.txt

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@@ -76,6 +76,7 @@ set(IGC_BUILD__SRC__CISACodeGen_Common
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"${CMAKE_CURRENT_SOURCE_DIR}/PromoteConstantStructs.cpp"
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"${CMAKE_CURRENT_SOURCE_DIR}/PromoteInt8Type.cpp"
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"${CMAKE_CURRENT_SOURCE_DIR}/SinkCommonOffsetFromGEP.cpp"
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"${CMAKE_CURRENT_SOURCE_DIR}/SplitLoads.cpp"
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"${CMAKE_CURRENT_SOURCE_DIR}/PruneUnusedArguments.cpp"
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"${CMAKE_CURRENT_SOURCE_DIR}/PullConstantHeuristics.cpp"
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"${CMAKE_CURRENT_SOURCE_DIR}/PushAnalysis.cpp"
@@ -201,6 +202,7 @@ set(IGC_BUILD__HDR__CISACodeGen_Common
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"${CMAKE_CURRENT_SOURCE_DIR}/ScalarizerCodeGen.hpp"
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"${CMAKE_CURRENT_SOURCE_DIR}/ShaderCodeGen.hpp"
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"${CMAKE_CURRENT_SOURCE_DIR}/ShaderUnits.hpp"
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"${CMAKE_CURRENT_SOURCE_DIR}/SplitLoads.h"
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"${CMAKE_CURRENT_SOURCE_DIR}/Simd32Profitability.hpp"
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"${CMAKE_CURRENT_SOURCE_DIR}/SinkCommonOffsetFromGEP.h"
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"${CMAKE_CURRENT_SOURCE_DIR}/TimeStatsCounter.h"

‎IGC/Compiler/CISACodeGen/ShaderCodeGen.cpp

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@@ -39,6 +39,7 @@ SPDX-License-Identifier: MIT
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#include "Compiler/CISACodeGen/MemOpt.h"
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#include "Compiler/CISACodeGen/MemOpt2.h"
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#include "Compiler/CISACodeGen/MergeUniformStores.hpp"
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#include "Compiler/CISACodeGen/SplitLoads.h"
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#include "Compiler/CISACodeGen/PreRARematFlag.h"
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#include "Compiler/CISACodeGen/PromoteConstantStructs.hpp"
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#include "Compiler/Optimizer/OpenCLPasses/Decompose2DBlockFuncs/Decompose2DBlockFuncs.hpp"
@@ -220,6 +221,10 @@ void AddAnalysisPasses(CodeGenContext& ctx, IGCPassManager& mpm)
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mpm.add(createMemOpt2Pass(16));
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}
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if (!isOptDisabled) {
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mpm.add(createSplitLoadsPass());
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}
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// only limited code-sinking to several shader-type
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// vs input has the URB-reuse issue to be resolved.
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// Also need to understand the performance benefit better.

‎IGC/Compiler/CISACodeGen/SplitLoads.cpp

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‎IGC/Compiler/CISACodeGen/SplitLoads.h

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/*========================== begin_copyright_notice ============================
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Copyright (C) 2025 Intel Corporation
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SPDX-License-Identifier: MIT
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============================= end_copyright_notice ===========================*/
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#pragma once
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#include "Compiler/CISACodeGen/IGCLivenessAnalysis.h"
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#include "Compiler/CodeGenPublic.h"
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#include "GenISAIntrinsics/GenIntrinsicInst.h"
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#include "common/LLVMWarningsPush.hpp"
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#include "llvm/ADT/SmallPtrSet.h"
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/IR/BasicBlock.h"
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#include "llvm/IR/Function.h"
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#include "llvm/IR/Instruction.h"
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#include "llvm/IR/Value.h"
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#include "llvm/Pass.h"
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#include "common/LLVMWarningsPop.hpp"
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#include <memory>
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#include <set>
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#include <utility>
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namespace llvm {
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class FunctionPass;
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}
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namespace IGC {
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namespace LS {
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/// A `struct` containing two dimensions of a block.
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struct Dims {
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unsigned grSize, numOfGr;
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unsigned size() const { return grSize * numOfGr; }
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bool operator<(const Dims &rhs) const {
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return grSize < rhs.grSize ||
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(grSize == rhs.grSize && numOfGr < rhs.numOfGr);
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}
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};
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using PossibleDims = std::set<Dims>;
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struct Config {
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Module *M = nullptr; // for debug info
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CodeGenContext *CGC = nullptr;
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IGCLivenessAnalysis *RPE = nullptr;
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bool isLegitW8 = false;
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unsigned sizeOfRegs_B = 0;
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unsigned numOfRegs = 0;
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unsigned defaultSimd = 0;
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unsigned actualSimd = 0;
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/// Turns on the splitting pass.
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bool enableLoadSplitting = IGC_IS_FLAG_ENABLED(LS_enableLoadSplitting);
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/// If `true`, the register pressure data is ignored and the pass splits all
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/// loads.
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bool ignoreSplitThreshold = IGC_IS_FLAG_ENABLED(LS_ignoreSplitThreshold);
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/// Minimal split size in terms of GRFs, used in determination of the possible
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/// split dimensions.
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unsigned minSplitSize_GRF = IGC_GET_FLAG_VALUE(LS_minSplitSize_GRF);
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/// Minimal split size in terms of vector elements (bit width-independent),
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/// used in determination of the possible split dimensions.
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unsigned minSplitSize_E = IGC_GET_FLAG_VALUE(LS_minSplitSize_E);
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/// If `ignoreSplitThreshold = false`, the pass splits loads in a given basic
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/// block only if the maximal register pressure exceeds total GRFs by this
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/// much.
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int splitThresholdDelta_GRF = IGC_GET_FLAG_VALUE(LS_splitThresholdDelta_GRF);
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/// Minimal split size in bytes, to be calculated from minSplitSize_GRF.
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unsigned minSplitSize_B = 0;
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/// Absolute split threshold in bytes.
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int splitThreshold_B = 0;
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Config(const Config &) = delete;
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Config(Config &&) = delete;
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/// Value of `SIMD` as reported by metadata.
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unsigned SIMD() const { return actualSimd ? actualSimd : defaultSimd; }
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static Config &get() {
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static Config config;
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return config;
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}
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bool initialize(Function *inF, CodeGenContext *inCGC,
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IGCLivenessAnalysis *inRPE);
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private:
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Config() = default;
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};
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Config &config();
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/// The class `LoadSplitter` is responsible for splitting loads in an LLVM
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/// function.
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class LoadSplitter {
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public:
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/// @brief Factory function to create an instance of `LoadSplitter`.
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/// @param inF LLVM function pointer.
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/// @param inCGC The code generation context.
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/// @param inRPE The register pressure estimator.
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static std::unique_ptr<LoadSplitter>
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Create(Function *inF, CodeGenContext *inCGC, IGCLivenessAnalysis *inRPE);
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LoadSplitter(const LoadSplitter &) = delete;
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LoadSplitter &operator=(const LoadSplitter &) = delete;
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/// @brief Returns `true` is the register pressure for the basic block exceeds
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/// the threshold given by the flag IGS_LS_splitThresholdDelta_GRF. The
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/// pressure must also exceed the goal, IGC_LS_goalPressureDelta_GRF.
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/// @param BB The basic block to check.
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bool isRPHigh(BasicBlock *BB);
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/// @brief Returns the set of all possible dimensions in which the load or AP
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/// loads can be split into.
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/// @param GII The load or the address payload to split. If `GII` is an AP
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/// Load, all loads associated with its AP are considered.
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PossibleDims possibleDims(GenIntrinsicInst *GII);
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/// @brief Splits the block load into the specified dimensions.
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/// @param GII The load or the address payload to split. If `GII` is an AP
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/// Load, all loads associated with its AP are considered.
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/// @param dims Size of the new blocks.
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/// @return Returns `true` on success, `false` otherwise.
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bool split(GenIntrinsicInst *GII, Dims dims);
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/// @brief Splits all loads in the basic block to the smallest size possible.
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/// @param BB The basic block.
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/// @return Returns `true` on success, `false` otherwise.
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bool splitAllToSmallest(BasicBlock *BB);
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private:
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LoadSplitter() = default;
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struct Impl;
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std::unique_ptr<Impl> impl;
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};
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} // namespace LS
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FunctionPass *createSplitLoadsPass();
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} // namespace IGC

‎IGC/Compiler/InitializePasses.h

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@@ -156,6 +156,7 @@ void initializeSPIRMetaDataTranslationPass(llvm::PassRegistry&);
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void initializeSplitStructurePhisPassPass(llvm::PassRegistry&);
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void initializeSpv2dBlockIOResolutionPass(llvm::PassRegistry&);
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void initializeSpvSubgroupMMAResolutionPass(llvm::PassRegistry&);
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void initializeSplitLoadsPass(llvm::PassRegistry&);
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void initializeStatelessToStatefulPass(llvm::PassRegistry&);
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void initializeSubGroupFuncsResolutionPass(llvm::PassRegistry&);
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void initializeSubGroupReductionPatternPass(llvm::PassRegistry&);

‎IGC/Compiler/tests/SplitLoads/LS-params.ll

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; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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;=========================== begin_copyright_notice ============================
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;
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; Copyright (C) 2025 Intel Corporation
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;
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; SPDX-License-Identifier: MIT
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;
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;============================ end_copyright_notice =============================
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; REQUIRES: regkeys
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; RUN: igc_opt -S --igc-split-loads -platformpvc --regkey=LS_enableLoadSplitting=1 --regkey=LS_ignoreSplitThreshold=1 --regkey=LS_minSplitSize_GRF=0 --regkey=LS_minSplitSize_E=0 %s | FileCheck %s --check-prefix=SPLIT
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; RUN: igc_opt -S --igc-split-loads -platformpvc --regkey=LS_enableLoadSplitting=1 --regkey=LS_ignoreSplitThreshold=1 --regkey=LS_minSplitSize_GRF=100 --regkey=LS_minSplitSize_E=0 %s | FileCheck %s --check-prefix=GRF
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; RUN: igc_opt -S --igc-split-loads -platformpvc --regkey=LS_enableLoadSplitting=1 --regkey=LS_ignoreSplitThreshold=1 --regkey=LS_minSplitSize_GRF=0 --regkey=LS_minSplitSize_E=4 %s | FileCheck %s --check-prefix=ELTS4
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; RUN: igc_opt -S --igc-split-loads -platformpvc --regkey=LS_enableLoadSplitting=1 --regkey=LS_ignoreSplitThreshold=1 --regkey=LS_minSplitSize_GRF=0 --regkey=LS_minSplitSize_E=8 %s | FileCheck %s --check-prefix=ELTS8
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; RUN: igc_opt -S --igc-split-loads -platformpvc --regkey=LS_enableLoadSplitting=1 --regkey=LS_ignoreSplitThreshold=1 --regkey=LS_minSplitSize_GRF=0 --regkey=LS_minSplitSize_E=16 %s | FileCheck %s --check-prefix=ELTS16
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; RUN: igc_opt -S --igc-split-loads -platformpvc --regkey=LS_enableLoadSplitting=1 --regkey=LS_ignoreSplitThreshold=0 --regkey=LS_splitThresholdDelta_GRF=-1000 %s | FileCheck %s --check-prefix=THRESHOLD
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declare spir_func void @fun_v4i32(<4 x i32>)
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declare spir_func <16 x i32> @llvm.genx.GenISA.LSC2DBlockRead.v16i32(i64, i32, i32, i32, i32, i32, i32, i32, i32, i32, i1, i1, i32)
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define spir_kernel void @test_threshold(i64 %ptr) {
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; SPLIT-LABEL: @test_threshold(
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; SPLIT-NEXT: [[TMP1:%.*]] = call <4 x i32> @llvm.genx.GenISA.LSC2DBlockRead.v4i32(i64 [[PTR:%.*]], i32 127, i32 63, i32 127, i32 0, i32 0, i32 32, i32 16, i32 4, i32 1, i1 false, i1 false, i32 0)
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; SPLIT-NEXT: [[TMP2:%.*]] = call <4 x i32> @llvm.genx.GenISA.LSC2DBlockRead.v4i32(i64 [[PTR]], i32 127, i32 63, i32 127, i32 0, i32 4, i32 32, i32 16, i32 4, i32 1, i1 false, i1 false, i32 0)
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; SPLIT-NEXT: [[TMP3:%.*]] = call <4 x i32> @llvm.genx.GenISA.LSC2DBlockRead.v4i32(i64 [[PTR]], i32 127, i32 63, i32 127, i32 0, i32 8, i32 32, i32 16, i32 4, i32 1, i1 false, i1 false, i32 0)
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; SPLIT-NEXT: [[TMP4:%.*]] = call <4 x i32> @llvm.genx.GenISA.LSC2DBlockRead.v4i32(i64 [[PTR]], i32 127, i32 63, i32 127, i32 0, i32 12, i32 32, i32 16, i32 4, i32 1, i1 false, i1 false, i32 0)
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; SPLIT-NEXT: call void @fun_v4i32(<4 x i32> [[TMP1]])
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; SPLIT-NEXT: call void @fun_v4i32(<4 x i32> [[TMP2]])
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; SPLIT-NEXT: call void @fun_v4i32(<4 x i32> [[TMP3]])
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; SPLIT-NEXT: call void @fun_v4i32(<4 x i32> [[TMP4]])
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; SPLIT-NEXT: ret void
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;
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; GRF-LABEL: @test_threshold(
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; GRF-NEXT: [[VEC1:%.*]] = call <16 x i32> @llvm.genx.GenISA.LSC2DBlockRead.v16i32(i64 [[PTR:%.*]], i32 127, i32 63, i32 127, i32 0, i32 0, i32 32, i32 16, i32 16, i32 1, i1 false, i1 false, i32 0)
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; GRF-NEXT: [[PICK1_1:%.*]] = shufflevector <16 x i32> [[VEC1]], <16 x i32> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
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; GRF-NEXT: [[PICK1_2:%.*]] = shufflevector <16 x i32> [[VEC1]], <16 x i32> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
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; GRF-NEXT: [[PICK1_3:%.*]] = shufflevector <16 x i32> [[VEC1]], <16 x i32> undef, <4 x i32> <i32 8, i32 9, i32 10, i32 11>
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; GRF-NEXT: [[PICK1_4:%.*]] = shufflevector <16 x i32> [[VEC1]], <16 x i32> undef, <4 x i32> <i32 12, i32 13, i32 14, i32 15>
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; GRF-NEXT: call void @fun_v4i32(<4 x i32> [[PICK1_1]])
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; GRF-NEXT: call void @fun_v4i32(<4 x i32> [[PICK1_2]])
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; GRF-NEXT: call void @fun_v4i32(<4 x i32> [[PICK1_3]])
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; GRF-NEXT: call void @fun_v4i32(<4 x i32> [[PICK1_4]])
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; GRF-NEXT: ret void
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;
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; ELTS4-LABEL: @test_threshold(
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; ELTS4-NEXT: [[TMP1:%.*]] = call <4 x i32> @llvm.genx.GenISA.LSC2DBlockRead.v4i32(i64 [[PTR:%.*]], i32 127, i32 63, i32 127, i32 0, i32 0, i32 32, i32 16, i32 4, i32 1, i1 false, i1 false, i32 0)
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; ELTS4-NEXT: [[TMP2:%.*]] = call <4 x i32> @llvm.genx.GenISA.LSC2DBlockRead.v4i32(i64 [[PTR]], i32 127, i32 63, i32 127, i32 0, i32 4, i32 32, i32 16, i32 4, i32 1, i1 false, i1 false, i32 0)
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; ELTS4-NEXT: [[TMP3:%.*]] = call <4 x i32> @llvm.genx.GenISA.LSC2DBlockRead.v4i32(i64 [[PTR]], i32 127, i32 63, i32 127, i32 0, i32 8, i32 32, i32 16, i32 4, i32 1, i1 false, i1 false, i32 0)
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; ELTS4-NEXT: [[TMP4:%.*]] = call <4 x i32> @llvm.genx.GenISA.LSC2DBlockRead.v4i32(i64 [[PTR]], i32 127, i32 63, i32 127, i32 0, i32 12, i32 32, i32 16, i32 4, i32 1, i1 false, i1 false, i32 0)
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; ELTS4-NEXT: call void @fun_v4i32(<4 x i32> [[TMP1]])
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; ELTS4-NEXT: call void @fun_v4i32(<4 x i32> [[TMP2]])
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; ELTS4-NEXT: call void @fun_v4i32(<4 x i32> [[TMP3]])
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; ELTS4-NEXT: call void @fun_v4i32(<4 x i32> [[TMP4]])
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; ELTS4-NEXT: ret void
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;
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; ELTS8-LABEL: @test_threshold(
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; ELTS8-NEXT: [[TMP1:%.*]] = call <8 x i32> @llvm.genx.GenISA.LSC2DBlockRead.v8i32(i64 [[PTR:%.*]], i32 127, i32 63, i32 127, i32 0, i32 0, i32 32, i32 16, i32 8, i32 1, i1 false, i1 false, i32 0)
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; ELTS8-NEXT: [[TMP2:%.*]] = extractelement <8 x i32> [[TMP1]], i64 0
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; ELTS8-NEXT: [[TMP3:%.*]] = insertelement <4 x i32> undef, i32 [[TMP2]], i64 0
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; ELTS8-NEXT: [[TMP4:%.*]] = extractelement <8 x i32> [[TMP1]], i64 1
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; ELTS8-NEXT: [[TMP5:%.*]] = insertelement <4 x i32> [[TMP3]], i32 [[TMP4]], i64 1
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; ELTS8-NEXT: [[TMP6:%.*]] = extractelement <8 x i32> [[TMP1]], i64 2
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; ELTS8-NEXT: [[TMP7:%.*]] = insertelement <4 x i32> [[TMP5]], i32 [[TMP6]], i64 2
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; ELTS8-NEXT: [[TMP8:%.*]] = extractelement <8 x i32> [[TMP1]], i64 3
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; ELTS8-NEXT: [[TMP9:%.*]] = insertelement <4 x i32> [[TMP7]], i32 [[TMP8]], i64 3
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; ELTS8-NEXT: [[TMP10:%.*]] = extractelement <8 x i32> [[TMP1]], i64 4
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; ELTS8-NEXT: [[TMP11:%.*]] = insertelement <4 x i32> undef, i32 [[TMP10]], i64 0
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; ELTS8-NEXT: [[TMP12:%.*]] = extractelement <8 x i32> [[TMP1]], i64 5
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; ELTS8-NEXT: [[TMP13:%.*]] = insertelement <4 x i32> [[TMP11]], i32 [[TMP12]], i64 1
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; ELTS8-NEXT: [[TMP14:%.*]] = extractelement <8 x i32> [[TMP1]], i64 6
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; ELTS8-NEXT: [[TMP15:%.*]] = insertelement <4 x i32> [[TMP13]], i32 [[TMP14]], i64 2
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; ELTS8-NEXT: [[TMP16:%.*]] = extractelement <8 x i32> [[TMP1]], i64 7
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; ELTS8-NEXT: [[TMP17:%.*]] = insertelement <4 x i32> [[TMP15]], i32 [[TMP16]], i64 3
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; ELTS8-NEXT: [[TMP18:%.*]] = call <8 x i32> @llvm.genx.GenISA.LSC2DBlockRead.v8i32(i64 [[PTR]], i32 127, i32 63, i32 127, i32 0, i32 8, i32 32, i32 16, i32 8, i32 1, i1 false, i1 false, i32 0)
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; ELTS8-NEXT: [[TMP19:%.*]] = extractelement <8 x i32> [[TMP18]], i64 0
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; ELTS8-NEXT: [[TMP20:%.*]] = insertelement <4 x i32> undef, i32 [[TMP19]], i64 0
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; ELTS8-NEXT: [[TMP21:%.*]] = extractelement <8 x i32> [[TMP18]], i64 1
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; ELTS8-NEXT: [[TMP22:%.*]] = insertelement <4 x i32> [[TMP20]], i32 [[TMP21]], i64 1
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; ELTS8-NEXT: [[TMP23:%.*]] = extractelement <8 x i32> [[TMP18]], i64 2
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; ELTS8-NEXT: [[TMP24:%.*]] = insertelement <4 x i32> [[TMP22]], i32 [[TMP23]], i64 2
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; ELTS8-NEXT: [[TMP25:%.*]] = extractelement <8 x i32> [[TMP18]], i64 3
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; ELTS8-NEXT: [[TMP26:%.*]] = insertelement <4 x i32> [[TMP24]], i32 [[TMP25]], i64 3
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; ELTS8-NEXT: [[TMP27:%.*]] = extractelement <8 x i32> [[TMP18]], i64 4
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; ELTS8-NEXT: [[TMP28:%.*]] = insertelement <4 x i32> undef, i32 [[TMP27]], i64 0
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; ELTS8-NEXT: [[TMP29:%.*]] = extractelement <8 x i32> [[TMP18]], i64 5
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; ELTS8-NEXT: [[TMP30:%.*]] = insertelement <4 x i32> [[TMP28]], i32 [[TMP29]], i64 1
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; ELTS8-NEXT: [[TMP31:%.*]] = extractelement <8 x i32> [[TMP18]], i64 6
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; ELTS8-NEXT: [[TMP32:%.*]] = insertelement <4 x i32> [[TMP30]], i32 [[TMP31]], i64 2
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; ELTS8-NEXT: [[TMP33:%.*]] = extractelement <8 x i32> [[TMP18]], i64 7
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; ELTS8-NEXT: [[TMP34:%.*]] = insertelement <4 x i32> [[TMP32]], i32 [[TMP33]], i64 3
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; ELTS8-NEXT: call void @fun_v4i32(<4 x i32> [[TMP9]])
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; ELTS8-NEXT: call void @fun_v4i32(<4 x i32> [[TMP17]])
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; ELTS8-NEXT: call void @fun_v4i32(<4 x i32> [[TMP26]])
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; ELTS8-NEXT: call void @fun_v4i32(<4 x i32> [[TMP34]])
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; ELTS8-NEXT: ret void
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;
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; ELTS16-LABEL: @test_threshold(
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; ELTS16-NEXT: [[VEC1:%.*]] = call <16 x i32> @llvm.genx.GenISA.LSC2DBlockRead.v16i32(i64 [[PTR:%.*]], i32 127, i32 63, i32 127, i32 0, i32 0, i32 32, i32 16, i32 16, i32 1, i1 false, i1 false, i32 0)
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; ELTS16-NEXT: [[PICK1_1:%.*]] = shufflevector <16 x i32> [[VEC1]], <16 x i32> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
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; ELTS16-NEXT: [[PICK1_2:%.*]] = shufflevector <16 x i32> [[VEC1]], <16 x i32> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
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; ELTS16-NEXT: [[PICK1_3:%.*]] = shufflevector <16 x i32> [[VEC1]], <16 x i32> undef, <4 x i32> <i32 8, i32 9, i32 10, i32 11>
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; ELTS16-NEXT: [[PICK1_4:%.*]] = shufflevector <16 x i32> [[VEC1]], <16 x i32> undef, <4 x i32> <i32 12, i32 13, i32 14, i32 15>
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; ELTS16-NEXT: call void @fun_v4i32(<4 x i32> [[PICK1_1]])
105+
; ELTS16-NEXT: call void @fun_v4i32(<4 x i32> [[PICK1_2]])
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; ELTS16-NEXT: call void @fun_v4i32(<4 x i32> [[PICK1_3]])
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; ELTS16-NEXT: call void @fun_v4i32(<4 x i32> [[PICK1_4]])
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; ELTS16-NEXT: ret void
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;
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; THRESHOLD-LABEL: @test_threshold(
111+
; THRESHOLD-NEXT: [[TMP1:%.*]] = call <4 x i32> @llvm.genx.GenISA.LSC2DBlockRead.v4i32(i64 [[PTR:%.*]], i32 127, i32 63, i32 127, i32 0, i32 0, i32 32, i32 16, i32 4, i32 1, i1 false, i1 false, i32 0)
112+
; THRESHOLD-NEXT: [[TMP2:%.*]] = call <4 x i32> @llvm.genx.GenISA.LSC2DBlockRead.v4i32(i64 [[PTR]], i32 127, i32 63, i32 127, i32 0, i32 4, i32 32, i32 16, i32 4, i32 1, i1 false, i1 false, i32 0)
113+
; THRESHOLD-NEXT: [[TMP3:%.*]] = call <4 x i32> @llvm.genx.GenISA.LSC2DBlockRead.v4i32(i64 [[PTR]], i32 127, i32 63, i32 127, i32 0, i32 8, i32 32, i32 16, i32 4, i32 1, i1 false, i1 false, i32 0)
114+
; THRESHOLD-NEXT: [[TMP4:%.*]] = call <4 x i32> @llvm.genx.GenISA.LSC2DBlockRead.v4i32(i64 [[PTR]], i32 127, i32 63, i32 127, i32 0, i32 12, i32 32, i32 16, i32 4, i32 1, i1 false, i1 false, i32 0)
115+
; THRESHOLD-NEXT: call void @fun_v4i32(<4 x i32> [[TMP1]])
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; THRESHOLD-NEXT: call void @fun_v4i32(<4 x i32> [[TMP2]])
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; THRESHOLD-NEXT: call void @fun_v4i32(<4 x i32> [[TMP3]])
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; THRESHOLD-NEXT: call void @fun_v4i32(<4 x i32> [[TMP4]])
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; THRESHOLD-NEXT: ret void
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;
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; DEFAULT-LABEL: @test_threshold(
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; DEFAULT-NEXT: [[TMP1:%.*]] = call <4 x i32> @llvm.genx.GenISA.LSC2DBlockRead.v4i32(i64 [[PTR:%.*]], i32 127, i32 63, i32 127, i32 0, i32 0, i32 32, i32 16, i32 4, i32 1, i1 false, i1 false, i32 0)
123+
; DEFAULT-NEXT: [[TMP2:%.*]] = call <4 x i32> @llvm.genx.GenISA.LSC2DBlockRead.v4i32(i64 [[PTR]], i32 127, i32 63, i32 127, i32 0, i32 4, i32 32, i32 16, i32 4, i32 1, i1 false, i1 false, i32 0)
124+
; DEFAULT-NEXT: [[TMP3:%.*]] = call <4 x i32> @llvm.genx.GenISA.LSC2DBlockRead.v4i32(i64 [[PTR]], i32 127, i32 63, i32 127, i32 0, i32 8, i32 32, i32 16, i32 4, i32 1, i1 false, i1 false, i32 0)
125+
; DEFAULT-NEXT: [[TMP4:%.*]] = call <4 x i32> @llvm.genx.GenISA.LSC2DBlockRead.v4i32(i64 [[PTR]], i32 127, i32 63, i32 127, i32 0, i32 12, i32 32, i32 16, i32 4, i32 1, i1 false, i1 false, i32 0)
126+
; DEFAULT-NEXT: call void @fun_v4i32(<4 x i32> [[TMP1]])
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; DEFAULT-NEXT: call void @fun_v4i32(<4 x i32> [[TMP2]])
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; DEFAULT-NEXT: call void @fun_v4i32(<4 x i32> [[TMP3]])
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; DEFAULT-NEXT: call void @fun_v4i32(<4 x i32> [[TMP4]])
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; DEFAULT-NEXT: ret void
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%vec1 = call <16 x i32> @llvm.genx.GenISA.LSC2DBlockRead.v16i32(i64 %ptr, i32 127, i32 63, i32 127, i32 0, i32 0, i32 32, i32 16, i32 16, i32 1, i1 false, i1 false, i32 0)
132+
%pick1.1 = shufflevector <16 x i32> %vec1, <16 x i32> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
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%pick1.2 = shufflevector <16 x i32> %vec1, <16 x i32> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
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%pick1.3 = shufflevector <16 x i32> %vec1, <16 x i32> undef, <4 x i32> <i32 8, i32 9, i32 10, i32 11>
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%pick1.4 = shufflevector <16 x i32> %vec1, <16 x i32> undef, <4 x i32> <i32 12, i32 13, i32 14, i32 15>
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call void @fun_v4i32(<4 x i32> %pick1.1)
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call void @fun_v4i32(<4 x i32> %pick1.2)
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call void @fun_v4i32(<4 x i32> %pick1.3)
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call void @fun_v4i32(<4 x i32> %pick1.4)
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ret void
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}

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