optimizations to global_id_offset/local_size implicit args

Compute workloads add following implicit arguments:
 1. payloadHeader - 8 x i32 packing global_id_offset (3 x i32),
    local_size (3 x i32) and 2 x i32 reserved.
 2. enqueued_local_size - 3 x i32

local_size is never used in favour of enqueued_local_size. In the end,
payloadHeader has unused 20 bytes.

This change introduces following optimizations:
 1. Reduces payloadHeader to 3 x i32, packing only global_id_offset.
 2. Removes global_id_offset and enqueued_local_size from finalizer
    and zeinfo if arguments are unused.

Author: pkwasnie-intel

IGC/AdaptorCommon/ImplicitArgs.cpp

@@ -24,7 +24,7 @@ using namespace IGC::IGCMD;
 static const std::vector<ImplicitArg> IMPLICIT_ARGS = {
     ImplicitArg(ImplicitArg::R0, "r0", ImplicitArg::INT, WIAnalysis::UNIFORM_THREAD, 8, ImplicitArg::ALIGN_GRF, false, GenISAIntrinsic::GenISA_getR0),
 
-    ImplicitArg(ImplicitArg::PAYLOAD_HEADER, "payloadHeader", ImplicitArg::INT, WIAnalysis::UNIFORM_WORKGROUP, 8, ImplicitArg::ALIGN_GRF, true, GenISAIntrinsic::GenISA_getPayloadHeader),
+    ImplicitArg(ImplicitArg::PAYLOAD_HEADER, "payloadHeader", ImplicitArg::INT, WIAnalysis::UNIFORM_WORKGROUP, 3, ImplicitArg::ALIGN_DWORD, true, GenISAIntrinsic::GenISA_getPayloadHeader),
     ImplicitArg(ImplicitArg::WORK_DIM, "workDim", ImplicitArg::INT, WIAnalysis::UNIFORM_GLOBAL, 1, ImplicitArg::ALIGN_DWORD, true, GenISAIntrinsic::GenISA_getWorkDim),
 
     ImplicitArg(ImplicitArg::NUM_GROUPS, "numWorkGroups", ImplicitArg::INT, WIAnalysis::UNIFORM_GLOBAL, 3, ImplicitArg::ALIGN_DWORD, true, GenISAIntrinsic::GenISA_getNumWorkGroups),

IGC/Compiler/CISACodeGen/OpenCLKernelCodeGen.cpp

@@ -907,16 +907,11 @@ namespace IGC
         switch (kernelArg->getArgType()) {
 
         case KernelArg::ArgType::IMPLICIT_PAYLOAD_HEADER:{
-            // PayloadHeader contains global work offset x,y,z and local size x,y,z
-            // global work offset, size is int32x3
-            uint cur_pos = payloadPosition;
+            // PayloadHeader contains global work offset x,y,z
+            // global work offset size is int32x3
             uint32_t size = iOpenCL::DATA_PARAMETER_DATA_SIZE * 3;
             zebin::ZEInfoBuilder::addPayloadArgumentImplicit(m_kernelInfo.m_zePayloadArgs,
-                zebin::PreDefinedAttrGetter::ArgType::global_id_offset, cur_pos, size);
-            cur_pos += size;
-            // local size, size is int32x3, the same as above
-            zebin::ZEInfoBuilder::addPayloadArgumentImplicit(m_kernelInfo.m_zePayloadArgs,
-                zebin::PreDefinedAttrGetter::ArgType::local_size, cur_pos, size);
+                zebin::PreDefinedAttrGetter::ArgType::global_id_offset, payloadPosition, size);
             break;
         }
         case KernelArg::ArgType::IMPLICIT_PRIVATE_BASE:
@@ -1512,17 +1507,15 @@ namespace IGC
             break;
 
         case KernelArg::ArgType::IMPLICIT_PAYLOAD_HEADER:
-            // PayloadHeader contains global work offset x,y,z and local size x,y,z -->
-            // total of 6 annotations, 3 of each type
-            for (int i = 0; i < 6; ++i)
+            // PayloadHeader contains global work offset x,y,z -->
+            // total of 3 annotations of each type
+            for (int i = 0; i < 3; ++i)
             {
                 auto constInput = std::make_unique<iOpenCL::ConstantInputAnnotation>();
 
                 DWORD sizeInBytes = iOpenCL::DATA_PARAMETER_DATA_SIZE;
 
-                constInput->ConstantType = (i < 3 ?
-                    iOpenCL::DATA_PARAMETER_GLOBAL_WORK_OFFSET :
-                    iOpenCL::DATA_PARAMETER_LOCAL_WORK_SIZE);
+                constInput->ConstantType = iOpenCL::DATA_PARAMETER_GLOBAL_WORK_OFFSET;
                 constInput->Offset = (i % 3) * sizeInBytes;
                 constInput->PayloadPosition = payloadPosition;
                 constInput->PayloadSizeInBytes = sizeInBytes;
@@ -2441,6 +2434,8 @@ namespace IGC
             bool IsUnusedArg =
                 (arg.getArgType() == KernelArg::ArgType::IMPLICIT_BUFFER_OFFSET ||
                 arg.getArgType() == KernelArg::ArgType::IMPLICIT_BINDLESS_OFFSET ||
+                arg.getArgType() == KernelArg::ArgType::IMPLICIT_PAYLOAD_HEADER || // contains global_id_offset
+                arg.getArgType() == KernelArg::ArgType::IMPLICIT_ENQUEUED_LOCAL_WORK_SIZE ||
                 arg.getArgType() == KernelArg::ArgType::IMPLICIT_BUFFER_SIZE) &&
                 arg.getArg()->use_empty();
 

IGC/Compiler/Optimizer/OpenCLPasses/KernelArgs/KernelArgs.cpp

@@ -802,6 +802,7 @@ KernelArgsOrder::KernelArgsOrder(InputType layout)
 
             KernelArg::ArgType::RUNTIME_VALUE,
             KernelArg::ArgType::IMPLICIT_PAYLOAD_HEADER,
+            KernelArg::ArgType::IMPLICIT_ENQUEUED_LOCAL_WORK_SIZE,
 
             KernelArg::ArgType::PTR_LOCAL,
             KernelArg::ArgType::PTR_GLOBAL,
@@ -823,7 +824,6 @@ KernelArgsOrder::KernelArgsOrder(InputType layout)
             KernelArg::ArgType::IMPLICIT_LOCAL_SIZE,
             KernelArg::ArgType::IMPLICIT_STAGE_IN_GRID_ORIGIN,
             KernelArg::ArgType::IMPLICIT_STAGE_IN_GRID_SIZE,
-            KernelArg::ArgType::IMPLICIT_ENQUEUED_LOCAL_WORK_SIZE,
             KernelArg::ArgType::IMPLICIT_BINDLESS_OFFSET,
 
             KernelArg::ArgType::IMPLICIT_IMAGE_HEIGHT,
@@ -928,6 +928,7 @@ KernelArgsOrder::KernelArgsOrder(InputType layout)
 
             KernelArg::ArgType::RUNTIME_VALUE,
             KernelArg::ArgType::IMPLICIT_PAYLOAD_HEADER,
+            KernelArg::ArgType::IMPLICIT_ENQUEUED_LOCAL_WORK_SIZE,
             KernelArg::ArgType::PTR_LOCAL,
             KernelArg::ArgType::PTR_GLOBAL,
             KernelArg::ArgType::PTR_CONSTANT,
@@ -947,7 +948,6 @@ KernelArgsOrder::KernelArgsOrder(InputType layout)
             KernelArg::ArgType::IMPLICIT_LOCAL_SIZE,
             KernelArg::ArgType::IMPLICIT_STAGE_IN_GRID_ORIGIN,
             KernelArg::ArgType::IMPLICIT_STAGE_IN_GRID_SIZE,
-            KernelArg::ArgType::IMPLICIT_ENQUEUED_LOCAL_WORK_SIZE,
             KernelArg::ArgType::IMPLICIT_BINDLESS_OFFSET,
 
             KernelArg::ArgType::IMPLICIT_ARG_BUFFER,

IGC/Compiler/Optimizer/OpenCLPasses/WIFuncs/WIFuncResolution.cpp

@@ -209,12 +209,14 @@ void WIFuncResolution::visitCallInst(CallInst& CI)
 
  PayloadHeader:
 
------------------------------------------------------------------------------------------------
-| Global    | Global    | Global    | Local     | Local     | Local     | Reserved  | Num       |
-| offset    | offset    | offset    | size      | size      | size      |           | HW        |
-| X         | Y         | Z         | X         | Y         | Z         |           | Threads   |
-| 32bit     | 32bit     | 32bit     | 32bit     | 32bit     | 32bit     |           | 32bit     |
- -----------------------------------------------------------------------------------------------
+ Note: PayloadHeader used to be 8xi32, but unused bytes got removed and now it is 3xi32.
+
+------------------------------------
+| Global    | Global    | Global    |
+| offset    | offset    | offset    |
+| X         | Y         | Z         |
+| 32bit     | 32bit     | 32bit     |
+ -----------------------------------
  <low>                                                                                     <high>
 
 *************************************************************************************************/
@@ -509,7 +511,7 @@ Value* WIFuncResolution::getGlobalOffset(CallInst& CI)
     // call i32 @__builtin_IB_get_global_offset(i32 %dim)
 
     // Creates:
-    // %globalOffset = extractelement <8 x i32> %payloadHeader, i32 %dim
+    // %globalOffset = extractelement <3 x i32> %payloadHeader, i32 %dim
 
     auto F = CI.getFunction();
     Value* V = m_implicitArgs.getImplicitArgValue(*F, ImplicitArg::PAYLOAD_HEADER, m_pMdUtils);

IGC/Compiler/tests/AddImplicitArgs/signatiure_changed_PayloadHeader-typed-pointers.ll

@@ -1,6 +1,6 @@
 ;=========================== begin_copyright_notice ============================
 ;
-; Copyright (C) 2017-2021 Intel Corporation
+; Copyright (C) 2017-2025 Intel Corporation
 ;
 ; SPDX-License-Identifier: MIT
 ;
@@ -21,5 +21,5 @@ define i32 @foo(i32 %x) nounwind {
 !4 =  !{ !"implicit_arg_desc",  !6}
 !6 =  !{i32 1}
 
-; CHECK:         define i32 @foo(i32 %x, <8 x i32> %payloadHeader)
+; CHECK:         define i32 @foo(i32 %x, <3 x i32> %payloadHeader)
 ; CHECK-NOT:    define i32 @foo(i32 %x)

IGC/Compiler/tests/AddImplicitArgs/signatiure_changed_PayloadHeader.ll

@@ -1,6 +1,6 @@
 ;=========================== begin_copyright_notice ============================
 ;
-; Copyright (C) 2017-2024 Intel Corporation
+; Copyright (C) 2017-2025 Intel Corporation
 ;
 ; SPDX-License-Identifier: MIT
 ;
@@ -22,5 +22,5 @@ define i32 @foo(i32 %x) nounwind {
 !4 =  !{ !"implicit_arg_desc",  !6}
 !6 =  !{i32 1}
 
-; CHECK:         define i32 @foo(i32 %x, <8 x i32> %payloadHeader)
+; CHECK:         define i32 @foo(i32 %x, <3 x i32> %payloadHeader)
 ; CHECK-NOT:    define i32 @foo(i32 %x)

IGC/Compiler/tests/AddImplicitArgs/signatiure_changed_R0_PayloadHeader_Localds-typed-pointers.ll

@@ -1,6 +1,6 @@
 ;=========================== begin_copyright_notice ============================
 ;
-; Copyright (C) 2017-2021 Intel Corporation
+; Copyright (C) 2017-2025 Intel Corporation
 ;
 ; SPDX-License-Identifier: MIT
 ;
@@ -25,5 +25,5 @@ define i32 @foo(i32 %x) nounwind {
 !9 =  !{i32 8}
 !10 =  !{i32 9}
 
-; CHECK:         define i32 @foo(i32 %x, <8 x i32> %r0, <8 x i32> %payloadHeader, i16 %localIdX, i16 %localIdY, i16 %localIdZ)
+; CHECK:         define i32 @foo(i32 %x, <8 x i32> %r0, <3 x i32> %payloadHeader, i16 %localIdX, i16 %localIdY, i16 %localIdZ)
 ; CHECK-NOT:    define i32 @foo(i32 %x)

IGC/Compiler/tests/AddImplicitArgs/signatiure_changed_R0_PayloadHeader_Localds.ll

@@ -1,6 +1,6 @@
 ;=========================== begin_copyright_notice ============================
 ;
-; Copyright (C) 2017-2024 Intel Corporation
+; Copyright (C) 2017-2025 Intel Corporation
 ;
 ; SPDX-License-Identifier: MIT
 ;
@@ -26,5 +26,5 @@ define i32 @foo(i32 %x) nounwind {
 !9 =  !{i32 8}
 !10 =  !{i32 9}
 
-; CHECK:         define i32 @foo(i32 %x, <8 x i32> %r0, <8 x i32> %payloadHeader, i16 %localIdX, i16 %localIdY, i16 %localIdZ)
+; CHECK:         define i32 @foo(i32 %x, <8 x i32> %r0, <3 x i32> %payloadHeader, i16 %localIdX, i16 %localIdY, i16 %localIdZ)
 ; CHECK-NOT:    define i32 @foo(i32 %x)

IGC/Compiler/tests/DebugInfo/AddImplicitArgs-typed-pointers.ll

@@ -1,6 +1,6 @@
 ;=========================== begin_copyright_notice ============================
 ;
-; Copyright (C) 2017-2024 Intel Corporation
+; Copyright (C) 2017-2025 Intel Corporation
 ;
 ; SPDX-License-Identifier: MIT
 ;
@@ -20,7 +20,7 @@ entry:
   store float 1.000000e+00, float addrspace(1)* %dst, align 4
   ret void
 
-; CHECK: define void @test(float addrspace(1)* %dst, <8 x i32> %r0, <8 x i32> %payloadHeader)
+; CHECK: define void @test(float addrspace(1)* %dst, <8 x i32> %r0, <3 x i32> %payloadHeader)
 ; CHECK: call void @llvm.dbg.value({{.*}})
 }
 

IGC/Compiler/tests/DebugInfo/AddImplicitArgs.ll

@@ -1,6 +1,6 @@
 ;=========================== begin_copyright_notice ============================
 ;
-; Copyright (C) 2017-2024 Intel Corporation
+; Copyright (C) 2017-2025 Intel Corporation
 ;
 ; SPDX-License-Identifier: MIT
 ;
@@ -21,7 +21,7 @@ entry:
   store float 1.000000e+00, ptr addrspace(1) %dst, align 4
   ret void
 
-; CHECK: define void @test(ptr addrspace(1) %dst, <8 x i32> %r0, <8 x i32> %payloadHeader)
+; CHECK: define void @test(ptr addrspace(1) %dst, <8 x i32> %r0, <3 x i32> %payloadHeader)
 ; CHECK: call void @llvm.dbg.value({{.*}})
 }
 

IGC/ocloc_tests/features/fp64_conv_emu/fp64_conv_emu.cl

@@ -14,7 +14,7 @@ SPDX-License-Identifier: MIT
 // CHECK-LABEL: @conversion_kernel(
 // CHECK-BASE: entry:
 // CHECK-BASE:  [[DPEmuFlag:%.*]] = alloca i32, align 4
-// CHECK-BASE:  [[TMP0:%.*]] = extractelement <8 x i32> %payloadHeader, i64 0
+// CHECK-BASE:  [[TMP0:%.*]] = extractelement <3 x i32> %payloadHeader, i64 0
 // CHECK-BASE:  [[TMP1:%.*]] = extractelement <3 x i32> %enqueuedLocalSize, i64 0
 // CHECK-BASE:  [[TMP2:%.*]] = extractelement <8 x i32> %r0, i64 1
 // CHECK-BASE:  [[MUL:%.*]] = mul i32 [[TMP1]], [[TMP2]]

IGC/ocloc_tests/features/fp64_conv_emu/fp64_conv_emu_fcmp.cl

@@ -13,7 +13,7 @@ SPDX-License-Identifier: MIT
 
 // CHECK-LABEL: @fcmp_kernel(
 // CHECK-BASE: entry:
-// CHECK-BASE:  [[TMP0:%.*]] = extractelement <8 x i32> %payloadHeader, i64 0
+// CHECK-BASE:  [[TMP0:%.*]] = extractelement <3 x i32> %payloadHeader, i64 0
 // CHECK-BASE:  [[TMP1:%.*]] = extractelement <3 x i32> %enqueuedLocalSize, i64 0
 // CHECK-BASE:  [[TMP2:%.*]] = extractelement <8 x i32> %r0, i64 1
 // CHECK-BASE:  [[MUL:%.*]] = mul i32 [[TMP1]], [[TMP2]]