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paigealesys_zuul
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Minor fixes for nullptr checking
Change-Id: I82f38e0cf7c376b56ed37be51346b6ca914e75c1
1 parent 51b40f9 commit 7298943

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3 files changed

+40
-26
lines changed

3 files changed

+40
-26
lines changed

visa/GraphColor.cpp

Lines changed: 20 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -5133,9 +5133,11 @@ void GraphColor::createLiveRanges(unsigned reserveSpillSize)
51335133
}
51345134
if (dcl->getIsPartialDcl())
51355135
{
5136-
G4_Declare * parentDcl = this->gra.getSplittedDeclare(dcl);
5137-
lrs[var->getId()]->setParentLRID(parentDcl->getRegVar()->getId());
5138-
lrs[var->getId()]->setIsPartialDcl();
5136+
if (G4_Declare * parentDcl = this->gra.getSplittedDeclare(dcl))
5137+
{
5138+
lrs[var->getId()]->setParentLRID(parentDcl->getRegVar()->getId());
5139+
lrs[var->getId()]->setIsPartialDcl();
5140+
}
51395141
}
51405142
if (dcl->getIsSplittedDcl())
51415143
{
@@ -5700,19 +5702,22 @@ bool GraphColor::assignColors(ColorHeuristic colorHeuristicGRF, bool doBankConfl
57005702
if (varSplitPass.isPartialDcl(lr->getDcl()))
57015703
{
57025704
parentDcl = varSplitPass.getParentDcl(lr->getDcl());
5703-
auto parentGRF = parentDcl->getRegVar()->getPhyReg();
5704-
if (!parentGRF && parentDcl->getRegVar()->isRegAllocPartaker())
5705-
{
5706-
parentGRF = lrs[parentDcl->getRegVar()->getId()]->getPhyReg();
5707-
}
5708-
if (parentGRF)
5705+
if (parentDcl)
57095706
{
5710-
auto siblingNum = varSplitPass.getSiblingNum(lr->getDcl());
5711-
auto parentGRFNum = parentGRF->asGreg()->getRegNum();
5712-
auto forbiddenStart = parentGRFNum + ((siblingNum + 1) * lr->getDcl()->getNumRows());
5713-
auto forbiddenEnd = parentGRFNum + parentDcl->getNumRows();
5714-
lr->markForbidden(forbiddenStart, forbiddenEnd - forbiddenStart);
5715-
skipParentIntf = true;
5707+
auto parentGRF = parentDcl->getRegVar()->getPhyReg();
5708+
if (!parentGRF && parentDcl->getRegVar()->isRegAllocPartaker())
5709+
{
5710+
parentGRF = lrs[parentDcl->getRegVar()->getId()]->getPhyReg();
5711+
}
5712+
if (parentGRF)
5713+
{
5714+
auto siblingNum = varSplitPass.getSiblingNum(lr->getDcl());
5715+
auto parentGRFNum = parentGRF->asGreg()->getRegNum();
5716+
auto forbiddenStart = parentGRFNum + ((siblingNum + 1) * lr->getDcl()->getNumRows());
5717+
auto forbiddenEnd = parentGRFNum + parentDcl->getNumRows();
5718+
lr->markForbidden(forbiddenStart, forbiddenEnd - forbiddenStart);
5719+
skipParentIntf = true;
5720+
}
57165721
}
57175722
}
57185723
}

visa/LocalRA.cpp

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2592,6 +2592,9 @@ void LinearScan::expireSplitParent(LocalLiveRange* lr)
25922592
// lr is a partial dcl
25932593
auto parentDcl = varSplit->getParentDcl(lr->getTopDcl());
25942594

2595+
if (parentDcl == nullptr)
2596+
return;
2597+
25952598
// Now check whether parent in in active set
25962599
LocalLiveRange* parentLR = nullptr;
25972600
for (auto activeLR : active)

visa/VarSplit.cpp

Lines changed: 17 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -506,21 +506,23 @@ void VarSplitPass::writeHints(G4_Declare* dcl, LiveRange** lrs)
506506
else if (isChild)
507507
{
508508
// Write hint to parent if its empty
509-
auto parentDcl = getParentDcl(dcl);
510-
auto idealParentGRF = getIdealAllocation(parentDcl, lrs);
511-
512-
if (idealParentGRF != 0 && parentDcl->getRegVar()->isRegAllocPartaker())
509+
if (auto parentDcl = getParentDcl(dcl))
513510
{
514-
lrs[parentDcl->getRegVar()->getId()]->setAllocHint(idealParentGRF);
515-
auto children = getChildren(getParentDcl(dcl));
516-
unsigned int i = 0;
517-
for (auto child : *children)
511+
auto idealParentGRF = getIdealAllocation(parentDcl, lrs);
512+
513+
if (idealParentGRF != 0 && parentDcl->getRegVar()->isRegAllocPartaker())
518514
{
519-
if (child->getRegVar()->isRegAllocPartaker())
515+
lrs[parentDcl->getRegVar()->getId()]->setAllocHint(idealParentGRF);
516+
auto children = getChildren(getParentDcl(dcl));
517+
unsigned int i = 0;
518+
for (auto child : *children)
520519
{
521-
lrs[child->getRegVar()->getId()]->setAllocHint(idealParentGRF + (i * child->getNumRows()));
520+
if (child->getRegVar()->isRegAllocPartaker())
521+
{
522+
lrs[child->getRegVar()->getId()]->setAllocHint(idealParentGRF + (i * child->getNumRows()));
523+
}
524+
i++;
522525
}
523-
i++;
524526
}
525527
}
526528
}
@@ -605,6 +607,10 @@ bool VarSplitPass::reallocParent(G4_Declare* child, LiveRange** lrs)
605607
return false;
606608

607609
auto parent = getParentDcl(child);
610+
611+
if (parent == nullptr)
612+
return false;
613+
608614
auto children = getChildren(parent);
609615

610616
auto baseRegNum = 0;

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