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symexpr handles or and shl
Improve symexpr to handle some special instructions: 1. or with a constant : change to add if it can be, and 2. shl by a constant : change to mul
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‎IGC/Compiler/CISACodeGen/SLMConstProp.cpp

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Original file line numberDiff line numberDiff line change
@@ -372,10 +372,36 @@ void SymbolicEvaluation::getSymExprOrConstant(const Value* V, SymExpr*& S, int64
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if (const ConstantInt * CI = dyn_cast<const ConstantInt>(V))
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{
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// symExpr handles symbols with the same bit size, thus sext/zext/trunc
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// are not handled. With this, a result from either signed or unsigned
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// integer operations will end up with the same bit pattern. Here, we
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// choose to use sext on constants.
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C = CI->getSExtValue();
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return;
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}
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// Used for nomalizing shift amount.
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// For example, i64, its type mask is 03F(63 = 64 - 1).
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auto getTypeMask = [](const Type* Ty) -> uint32_t {
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// For simplicity, only handle type whose size is power of 2.
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uint32_t nbits = Ty->getScalarSizeInBits();
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if (nbits > 0 && isPowerOf2_32(nbits))
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return (nbits - 1);
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return 0;
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};
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// Return value:
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// Shift amount: if it is valid and greater than 0
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// 0 : invalid
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auto getShlAmt = [&getTypeMask](const Instruction* ShlInst) -> uint32_t {
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IGC_ASSERT(ShlInst->getOpcode() == Instruction::Shl);
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uint32_t shtAmtMask = getTypeMask(ShlInst->getType());
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ConstantInt* cI = cast<ConstantInt>(ShlInst->getOperand(1));
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if (cI && shtAmtMask > 0)
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return (uint32_t)(cI->getZExtValue() & shtAmtMask);
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return 0;
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};
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// Instructions/Operators handled for now:
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// GEP
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// bitcast (inttoptr, ptrtoint, etc)
@@ -515,6 +541,35 @@ void SymbolicEvaluation::getSymExprOrConstant(const Value* V, SymExpr*& S, int64
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}
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break;
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}
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case Instruction::Or:
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{
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// Check if it is actually an add.
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//
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// %mul = shl nuw nsw i64 %v, 1
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// %add = or i64 %mul, 1
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// --> %add = add %mul, 1
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const Value* V0 = Op->getOperand(0);
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const Value* V1 = Op->getOperand(1);
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getSymExprOrConstant(V0, S0, C0);
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getSymExprOrConstant(V1, S1, C1);
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if (!S0 && !S1) {
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C = C0 | C1;
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return;
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}
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// Case: 'or V0 Const' or 'or const V1'
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if ((S0 && !S1) || (!S0 && S1)) {
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const Value* tV = (S0 ? V0 : V1);
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const uint64_t tC = (uint64_t)(S0 ? C1 : C0);
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const Instruction* tI = dyn_cast<Instruction>(tV);
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if (tI && tI->getOpcode() == Instruction::Shl) {
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uint32_t shtAmt = getShlAmt(tI);
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if (shtAmt > 0 && (1ull << shtAmt) > tC)
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S = add(S0 ? S0 : S1, tC);
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}
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}
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break;
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}
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case Instruction::Mul:
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{
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const Value* V0 = Op->getOperand(0);
@@ -538,7 +593,34 @@ void SymbolicEvaluation::getSymExprOrConstant(const Value* V, SymExpr*& S, int64
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break;
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}
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case Instruction::Shl:
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{
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// shl is a mul
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// shl a, b, 2
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// -> mul a, b, (1 << 2)
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const Value* V0 = Op->getOperand(0);
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const Value* V1 = Op->getOperand(1);
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getSymExprOrConstant(V0, S0, C0);
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getSymExprOrConstant(V1, S1, C1);
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uint32_t shtAmtMask = getTypeMask(V->getType());
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if (shtAmtMask == 0) // sanity
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break;
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if (!S1) {
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C1 = (C1 & shtAmtMask);
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}
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if (!S0 && !S1) {
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C = (C0 << C1);
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return;
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}
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if (!S1) {
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uint64_t tC = (1ull << C1);
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S = mul(S0, tC);
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}
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break;
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}
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case Instruction::BitCast:
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case Instruction::IntToPtr:
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case Instruction::PtrToInt:

‎IGC/Compiler/tests/LdStCombine/store_address_or_inst.ll

Lines changed: 58 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,58 @@
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;=========================== begin_copyright_notice ============================
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;
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; Copyright (C) 2017-2023 Intel Corporation
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;
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; SPDX-License-Identifier: MIT
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;
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;============================ end_copyright_notice =============================
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; Given a0 = shl a, 1
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; a1 = getelementptr inbounds <2 x i32>, <2 x i32> addrspace(1)* %d, i64 %a0
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; store <2 x i32> %v0, <2 x i32> addrspace(1)* %a1, align 8
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; a2 = or i64 %a0, 1
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; a3 = getelementptr inbounds <2 x i32>, <2 x i32> addrspace(1)* %d, i64 %a2
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; store <2 x i32> %v1, <2 x i32> addrspace(1)* %a3, align 8
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; combined into
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; store <4xi32>
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;
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; This is to test that symbolic expression can handle 'or' and 'shl' instructions
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;
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; CHECK-LABEL: target datalayout
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; CHECK: %__StructSOALayout_ = type <{ <2 x i32>, <2 x i32> }>
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; CHECK-LABEL: define spir_kernel void @test_st
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; CHECK: load <4 x i32>,
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; CHECK: [[TMP1:%.*]] = insertvalue %__StructSOALayout_ undef, <2 x i32> %{{.*}}, 0
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; CHECK: [[TMP2:%.*]] = insertvalue %__StructSOALayout_ [[TMP1]], <2 x i32> %{{.*}}, 1
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; CHECK: [[TMP3:%.*]] = call <4 x i32> @llvm.genx.GenISA.bitcastfromstruct.v4i32.__StructSOALayout_(%__StructSOALayout_ [[TMP2]])
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; CHECK: store <4 x i32> [[TMP3]]
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; CHECK: ret void
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target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v16:16:16-v24:32:32-v32:32:32-v48:64:64-v64:64:64-v96:128:128-v128:128:128-v192:256:256-v256:256:256-v512:512:512-v1024:1024:1024-n8:16:32"
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target triple = "spir64-unknown-unknown"
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; Function Attrs: convergent nounwind
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define spir_kernel void @test_st(<2 x i32> addrspace(1)* %d, <4 x i32> addrspace(1)* %s, <8 x i32> %r0, <8 x i32> %payloadHeader, <3 x i32> %enqueuedLocalSize, i16 %localIdX, i16 %localIdY, i16 %localIdZ) #0 {
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entry:
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%payloadHeader.scalar = extractelement <8 x i32> %payloadHeader, i32 0
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%enqueuedLocalSize.scalar = extractelement <3 x i32> %enqueuedLocalSize, i32 0
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%r0.scalar17 = extractelement <8 x i32> %r0, i32 1
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%mul.i.i.i = mul i32 %enqueuedLocalSize.scalar, %r0.scalar17
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%localIdX2 = zext i16 %localIdX to i32
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%add.i.i.i = add i32 %mul.i.i.i, %localIdX2
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%add4.i.i.i = add i32 %add.i.i.i, %payloadHeader.scalar
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%conv.i.i.i = zext i32 %add4.i.i.i to i64
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%mul = shl nuw nsw i64 %conv.i.i.i, 1
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%arrayidx = getelementptr inbounds <4 x i32>, <4 x i32> addrspace(1)* %s, i64 %mul
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%0 = load <4 x i32>, <4 x i32> addrspace(1)* %arrayidx, align 16
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%vecinit1.assembled.vect36 = shufflevector <4 x i32> %0, <4 x i32> undef, <2 x i32> <i32 0, i32 1>
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%vecinit4.assembled.vect37 = shufflevector <4 x i32> %0, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
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%arrayidx5 = getelementptr inbounds <2 x i32>, <2 x i32> addrspace(1)* %d, i64 %mul
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store <2 x i32> %vecinit1.assembled.vect36, <2 x i32> addrspace(1)* %arrayidx5, align 8
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%add = or i64 %mul, 1
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%arrayidx6 = getelementptr inbounds <2 x i32>, <2 x i32> addrspace(1)* %d, i64 %add
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store <2 x i32> %vecinit4.assembled.vect37, <2 x i32> addrspace(1)* %arrayidx6, align 8
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ret void
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}

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