Add some IGC and vISA testing support

- Add IGC flag "DisableConstBaseGlobalBaseArg" to force relocations
  instead of implicit args constBase and globalBase, for the testing
  purpose
- Introduce "bool VRTEnbale" GRFMode::Config to indicate if the Config
  can participate VRT (regSharingHeuristics)

Author: DianaChen

IGC/Compiler/Optimizer/OpenCLPasses/ProgramScopeConstants/ProgramScopeConstantAnalysis.cpp

@@ -264,12 +264,18 @@ bool ProgramScopeConstantAnalysis::runOnModule(Module& M)
     // Stackcalls:
     //  Stackcall ABI does not allow implicit args, so rely on relocation for global variable access
 
+    // TODO: Plan to disable ConstBase and GlobalBase implicit arguments on PVC+.
+    // StatelessToStateful pass is not enabled for most of the cases so there
+    // is no benefit to add the implicit arguments. Const/Global variables
+    // access can just go through relocations.
+
     // Workaround: When there is stringConstants in the module, do not insert
     // implicit arguments to prevent const vars getting promoted
     // at statelessToStateful pass. In zebin path, stateful promotion
     // of const vars can't work well with printf strings.
     bool skipConstAndGlobalBaseArgs =
-             Ctx->enableZEBinary() && !m_pModuleMd->stringConstants.empty();
+          IGC_IS_FLAG_ENABLED(DisableConstBaseGlobalBaseArg) ||
+          (Ctx->enableZEBinary() && !m_pModuleMd->stringConstants.empty());
 
     if (!skipConstAndGlobalBaseArgs && hasInlineConstantBuffer)
     {

IGC/common/igc_flags.h

@@ -227,6 +227,7 @@ DECLARE_IGC_REGKEY(bool, EnablePlatformFenceOpt,        true,  "Force DG2 only f
 DECLARE_IGC_REGKEY(bool, EnableSLMConstProp,            true,   "Enable SLM constant propagation (compute shader only).", false)
 DECLARE_IGC_REGKEY(bool, EnableStatelessToStateful,    true,  "Enable Stateless To Stateful transformation for global and constant address space in OpenCL kernels", false)
 DECLARE_IGC_REGKEY(bool, EnableStatefulToken,           true,  "Enable generating patch token to indicate a ptr argument is fully converted to stateful (temporary)", false)
+DECLARE_IGC_REGKEY(bool, DisableConstBaseGlobalBaseArg, false,  "Do no generate kernel implicit arguments: constBase and globalBase", false)
 DECLARE_IGC_REGKEY(bool, EnableGenUpdateCB,             false, "Enable derived constant optimization.", false)
 DECLARE_IGC_REGKEY(bool, EnableGenUpdateCBResInfo,      false, "Enable derived constant optimization with resinfo.", false)
 DECLARE_IGC_REGKEY(bool, EnableHighestSIMDForNoSpill,   false,   "When there is no spill choose highest SIMD (compute shader only).", false)

visa/G4_Kernel.cpp

@@ -620,11 +620,11 @@ void G4_Kernel::calculateSimdSize() {
 // Updates kernel's related structures to large GRF
 //
 bool G4_Kernel::updateKernelToLargerGRF() {
-  if (numRegTotal == grfMode.getMaxGRF())
+  if (numRegTotal == grfMode.getVRTMaxGRF())
     return false;
 
   // Scale number of GRFs, Acc, SWSB tokens.
-  setKernelParameters(grfMode.getLargerGRF());
+  setKernelParameters(grfMode.getVRTLargerGRF());
   fg.builder->rebuildPhyRegPool(getNumRegTotal());
   return true;
 }
@@ -633,11 +633,11 @@ bool G4_Kernel::updateKernelToLargerGRF() {
 // Updates kernel's related structures to smaller GRF
 //
 bool G4_Kernel::updateKernelToSmallerGRF() {
-  if (numRegTotal == grfMode.getMinGRF())
+  if (numRegTotal == grfMode.getVRTMinGRF())
     return false;
 
   // Scale number of GRFs, Acc, SWSB tokens.
-  setKernelParameters(grfMode.getSmallerGRF());
+  setKernelParameters(grfMode.getVRTSmallerGRF());
   fg.builder->rebuildPhyRegPool(getNumRegTotal());
   return true;
 }
@@ -1739,6 +1739,7 @@ void G4_Kernel::emitDeviceAsmInstructionsIga(std::ostream &os,
     return;
 
   iga_gen_t igaPlatform = getIGAPlatform(getPlatform());
+
   const iga::Model *igaModel =
       iga::Model::LookupModel(iga::ToPlatform(igaPlatform));
   iga::SWSB_ENCODE_MODE swsbEncodeMode = igaModel->getSWSBEncodeMode();
@@ -2048,23 +2049,24 @@ unsigned G4_Kernel::getComputeFFIDGP1NextOff() const {
 
 
 // GRF modes supported by HW
+// There must be at least one Config that is VRTEnable for each platform
 GRFMode::GRFMode(const TARGET_PLATFORM platform, Options *op) : options(op) {
   switch (platform) {
   case Xe_XeHPSDV:
   case Xe_DG2:
   case Xe_MTL:
     configs.resize(2);
     // Configurations with <numGRF, numThreads, SWSBTokens, numAcc>
-    configs[0] = {128, 8, 16, 4};
-    configs[1] = {256, 4, 16, 8};
+    configs[0] = Config(128, 8, 16, 4);
+    configs[1] = Config(256, 4, 16, 8);
     defaultMode = 0;
     break;
   case Xe_PVC:
   case Xe_PVCXT:
     configs.resize(2);
     // Configurations with <numGRF, numThreads, SWSBTokens, numAcc>
-    configs[0] = {128, 8, 16, 4};
-    configs[1] = {256, 4, 32, 8};
+    configs[0] = Config(128, 8, 16, 4);
+    configs[1] = Config(256, 4, 32, 8);
     defaultMode = 0;
     break;
   default:
@@ -2082,7 +2084,8 @@ unsigned GRFMode::findModeByRegPressure(unsigned maxRP, unsigned largestInputReg
   unsigned i = 0, newGRF = 0;
   // find appropiate GRF based on reg pressure
   for (; i < size; i++) {
-    if (maxRP <= configs[i].numGRF && largestInputReg <= configs[i].numGRF) {
+    if (configs[i].VRTEnable && maxRP <= configs[i].numGRF &&
+        largestInputReg <= configs[i].numGRF) {
       newGRF = configs[i].numGRF;
       break;
     }
@@ -2091,7 +2094,7 @@ unsigned GRFMode::findModeByRegPressure(unsigned maxRP, unsigned largestInputReg
   // if not found, pressure is too high
   // set largest grf mode
   if (i == size)
-    newGRF = getMaxGRF();
+    newGRF = getVRTMaxGRF();
 
   return newGRF;
 }

visa/G4_Kernel.hpp

@@ -16,6 +16,7 @@ SPDX-License-Identifier: MIT
 #include "include/gtpin_IGC_interface.h"
 #include "Assertions.h"
 
+#include <algorithm>
 #include <cstdint>
 #include <iostream>
 #include <map>
@@ -150,20 +151,8 @@ class GRFMode {
   unsigned findModeByRegPressure(unsigned maxRP, unsigned largestInputReg);
 
   unsigned getNumGRF() const { return configs[currentMode].numGRF; }
-  unsigned getMinGRF() const { return configs[0].numGRF; }
-  unsigned getMaxGRF() const {
-    return configs[configs.size() - 1].numGRF;
-  }
   unsigned getDefaultGRF() const { return configs[defaultMode].numGRF; }
   void setDefaultGRF() { currentMode = defaultMode; }
-  unsigned getLargerGRF() const {
-    return currentMode + 1 < configs.size() ? configs[currentMode + 1].numGRF
-                                            : configs[currentMode].numGRF;
-  }
-  unsigned getSmallerGRF() const {
-    return (signed)currentMode - 1 >= 0 ? configs[currentMode - 1].numGRF
-                                        : configs[currentMode].numGRF;
-  }
 
   unsigned getNumThreads() const { return configs[currentMode].numThreads; }
   unsigned getMinNumThreads() const {
@@ -180,13 +169,51 @@ class GRFMode {
 
   unsigned getNumAcc() const { return configs[currentMode].numAcc; }
 
+  // ----- helper functions for regSharingHeuristics (VRT) ----- //
+  unsigned getVRTMinGRF() const {
+    auto found = std::find_if(configs.begin(), configs.end(),
+                              [](const Config &c) { return c.VRTEnable; });
+    return found->numGRF;
+  }
+
+  unsigned getVRTMaxGRF() const {
+    auto found = std::find_if(configs.rbegin(), configs.rend(),
+                              [](const Config &c) { return c.VRTEnable; });
+    return found->numGRF;
+  }
+
+  unsigned getVRTLargerGRF() const {
+    // find the first larger mode that's available for VRT
+    for (auto i = currentMode + 1; i < configs.size(); ++i) {
+      if (configs[i].VRTEnable)
+        return configs[i].numGRF;
+    }
+    return configs[currentMode].numGRF;
+  }
+
+  unsigned getVRTSmallerGRF() const {
+    for (auto i = currentMode - 1; i >= 0 ; --i) {
+      if (configs[i].VRTEnable)
+        return configs[i].numGRF;
+    }
+    return configs[currentMode].numGRF;
+  }
+
 private:
   // Parameters associated to a GRF mode
   struct Config {
+    constexpr Config()
+        : numGRF(0), numThreads(0), numSWSB(0), numAcc(0), VRTEnable(false) {}
+    constexpr Config(unsigned NumGRF, unsigned NumThreads, unsigned NumSWSB,
+                     unsigned NumAcc, bool enableForVRT = true)
+        : numGRF(NumGRF), numThreads(NumThreads), numSWSB(NumSWSB),
+          numAcc(NumAcc), VRTEnable(enableForVRT) {}
     unsigned numGRF;
     unsigned numThreads;
     unsigned numSWSB;
     unsigned numAcc;
+    // if the config can be used by regSharingHeuristics
+    bool     VRTEnable;
   };
   // Vector configs maintains all the GRF modes available for the platform
   // being compiled.

visa/LocalScheduler/G4_Sched.cpp

@@ -714,8 +714,8 @@ bool preRA_RegSharing::run(unsigned &KernelPressure) {
     unsigned BBRP = rp.getPressure(bb);
 
     unsigned UpperBoundGRF = 0;
-    if (GRFdecreased && KernelPressure < kernel.grfMode.getMaxGRF())
-      UpperBoundGRF = kernel.grfMode.getLargerGRF();
+    if (GRFdecreased && KernelPressure < kernel.grfMode.getVRTMaxGRF())
+      UpperBoundGRF = kernel.grfMode.getVRTLargerGRF();
     Changed |= S.scheduleBlockForLatency(BBRP, Changed, UpperBoundGRF);
   }
 

visa/PrologEpilog.cpp

@@ -357,16 +357,16 @@ class PayloadLoader
       r0(
         b.createHardwiredDeclare(
           k.numEltPerGRF<Type_UD>(), Type_UD, 0, 0)),
-      rtmp(
-        b.createHardwiredDeclare(
-          k.numEltPerGRF<Type_UD>(), Type_UD,
-          k.getNumRegTotal() - 1, 0)),
       perThreadLoadStartGRF(
         k.getOptions()->getuInt32Option(vISA_loadThreadPayloadStartReg)),
       numPerThreadGRF(
         AlignUp(k.getInt32KernelAttr(Attributes::ATTR_PerThreadInputSize),
                 k.numEltPerGRF<Type_UB>()) / k.numEltPerGRF<Type_UB>())
   {
+
+    auto rtmpRegNum = k.getNumRegTotal() - 1;
+    rtmp = b.createHardwiredDeclare(k.numEltPerGRF<Type_UD>(), Type_UD, rtmpRegNum, 0);
+
     r0->setName("r0");
     rtmp->setName("rtmp");