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pratikasharigcbot
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Fix an incorrect condition when deciding if an unreferenced dcl can be
removed from list.
1 parent 64a79bc commit 81b88fa

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9 files changed

+57
-23
lines changed

9 files changed

+57
-23
lines changed

IGC/Compiler/CISACodeGen/CISABuilder.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -3869,7 +3869,7 @@ namespace IGC
38693869
}
38703870

38713871
if ((context->type == ShaderType::OPENCL_SHADER || context->type == ShaderType::COMPUTE_SHADER) &&
3872-
VISAPlatform >= GENX_SKL && IGC_IS_FLAG_ENABLED(EnablePreemption))
3872+
m_program->m_Platform->preemptionSupported() && IGC_IS_FLAG_ENABLED(EnablePreemption))
38733873
{
38743874
SaveOption(vISA_enablePreemption, true);
38753875
}

IGC/Compiler/CISACodeGen/Platform.hpp

Lines changed: 7 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -711,6 +711,13 @@ bool supportHeaderRTW() const
711711
{
712712
return true;
713713
}
714+
715+
bool preemptionSupported() const
716+
{
717+
718+
return GetPlatformFamily() >= IGFX_GEN9_CORE;
719+
};
720+
714721
};
715722

716723
}//namespace IGC

visa/BuildIRImpl.cpp

Lines changed: 8 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -675,23 +675,20 @@ void IR_Builder::createPreDefinedVars()
675675

676676
void IR_Builder::createBuiltinDecls()
677677
{
678-
678+
// realR0 is always tied to physical r0
679679
auto numR0DW = numEltPerGRF<Type_UD>();
680-
builtinR0 = createDeclareNoLookup(
681-
"BuiltinR0",
680+
realR0 = createDeclareNoLookup(
681+
"BuiltInR0",
682682
G4_INPUT,
683683
numR0DW,
684684
1,
685685
Type_UD);
686-
builtinR0->getRegVar()->setPhyReg(phyregpool.getGreg(0), 0);
687-
realR0 = builtinR0;
686+
realR0->getRegVar()->setPhyReg(phyregpool.getGreg(0), 0);
688687

689-
if (m_options->getOption(vISA_enablePreemption))
690-
{
691-
G4_Declare *R0CopyDcl = createTempVar(numR0DW, Type_UD, GRFALIGN);
692-
builtinR0 = R0CopyDcl;
693-
R0CopyDcl->setDoNotSpill();
694-
}
688+
// builtinR0 either gets allocated to r0 or to a different
689+
// register depending on conditions in RA.
690+
builtinR0 = createTempVar(numR0DW, Type_UD, GRFALIGN, "R0_Copy");
691+
builtinR0->setDoNotSpill();
695692

696693
builtinA0 = createDeclareNoLookup(
697694
"BuiltinA0",

visa/GraphColor.cpp

Lines changed: 2 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -9545,11 +9545,8 @@ int GlobalRA::coloringRegAlloc()
95459545

95469546
// bind builtinR0 to the reserved stack call ABI GRF so that caller and
95479547
// callee can agree on which GRF to use for r0
9548-
if (builder.getOption(vISA_enablePreemption))
9549-
{
9550-
builder.getBuiltinR0()->getRegVar()->setPhyReg(
9551-
builder.phyregpool.getGreg(kernel.getThreadHeaderGRF()), 0);
9552-
}
9548+
builder.getBuiltinR0()->getRegVar()->setPhyReg(
9549+
builder.phyregpool.getGreg(kernel.getThreadHeaderGRF()), 0);
95539550
}
95549551

95559552
if (!isReRAPass())

visa/LinearScanRA.cpp

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -785,7 +785,6 @@ void LinearScanRA::preRAAnalysis()
785785
const Options* opt = builder.getOptions();
786786
if (kernel.getInt32KernelAttr(Attributes::ATTR_Target) != VISA_3D ||
787787
opt->getOption(vISA_enablePreemption) ||
788-
(kernel.fg.getHasStackCalls() || kernel.fg.getIsStackCallFunc()) ||
789788
opt->getOption(vISA_ReserveR0))
790789
{
791790
pregs->setR0Forbidden();

visa/LocalRA.cpp

Lines changed: 1 addition & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -298,7 +298,6 @@ void LocalRA::preLocalRAAnalysis()
298298
const Options *opt = builder.getOptions();
299299
if (kernel.getInt32KernelAttr(Attributes::ATTR_Target) != VISA_3D ||
300300
opt->getOption(vISA_enablePreemption) ||
301-
stackCallRegSize > 0 ||
302301
opt->getOption(vISA_ReserveR0))
303302
{
304303
pregs->setR0Forbidden();
@@ -998,8 +997,7 @@ void GlobalRA::removeUnreferencedDcls()
998997
return (dcl->getRegFile() == G4_GRF || dcl->getRegFile() == G4_INPUT) &&
999998
getNumRefs(dcl) == 0 &&
1000999
dcl->getRegVar()->isPhyRegAssigned() == false &&
1001-
!(kernel.fg.builder->getOption(vISA_enablePreemption) &&
1002-
dcl == kernel.fg.builder->getBuiltinR0())
1000+
dcl != kernel.fg.builder->getBuiltinR0()
10031001
;
10041002
};
10051003

visa/Optimizer.cpp

Lines changed: 35 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -168,6 +168,17 @@ void Optimizer::regAlloc()
168168

169169
fg.prepareTraversal();
170170

171+
// realR0 and BuiltInR0 are 2 different dcls.
172+
// realR0 is always tied to physical r0.
173+
// if copy of r0 isnt needed then set latter to r0 as well.
174+
// if copy of r0 is required, then let RA decide allocation of BuiltInR0.
175+
if (!R0CopyNeeded())
176+
{
177+
// when no copy is needed, make BuiltInR0 an alias of realR0
178+
builder.getBuiltinR0()->setAliasDeclare(builder.getRealR0(), 0);
179+
builder.getBuiltinR0()->getRegVar()->setPhyReg(builder.getRealR0()->getRegVar()->getPhyReg(), 0);
180+
}
181+
171182
//
172183
// assign registers
173184
//
@@ -1022,7 +1033,7 @@ void Optimizer::initOptimizations()
10221033
INITIALIZE_PASS(dumpPayload, vISA_dumpPayload, TimerID::MISC_OPTS);
10231034
INITIALIZE_PASS(normalizeRegion, vISA_EnableAlways, TimerID::MISC_OPTS);
10241035
INITIALIZE_PASS(collectStats, vISA_EnableAlways, TimerID::MISC_OPTS);
1025-
INITIALIZE_PASS(createR0Copy, vISA_enablePreemption, TimerID::MISC_OPTS);
1036+
INITIALIZE_PASS(createR0Copy, vISA_EnableAlways, TimerID::MISC_OPTS);
10261037
INITIALIZE_PASS(initializePayload, vISA_InitPayload, TimerID::NUM_TIMERS);
10271038
INITIALIZE_PASS(cleanupBindless, vISA_enableCleanupBindless, TimerID::OPTIMIZER);
10281039
INITIALIZE_PASS(countGRFUsage, vISA_PrintRegUsage, TimerID::MISC_OPTS);
@@ -1416,6 +1427,23 @@ void Optimizer::accSubPostSchedule()
14161427
accSub.run();
14171428
}
14181429

1430+
bool Optimizer::R0CopyNeeded()
1431+
{
1432+
if (kernel.getOption(vISA_enablePreemption))
1433+
{
1434+
return true;
1435+
}
1436+
1437+
if (builder.getIsKernel() && kernel.fg.getHasStackCalls())
1438+
{
1439+
// As per VISA ABI, last register in GRF file should
1440+
// contain copy of r0.
1441+
return true;
1442+
}
1443+
1444+
return false;
1445+
}
1446+
14191447
int Optimizer::optimization()
14201448
{
14211449
// remove redundant message headers.
@@ -7428,6 +7456,12 @@ bool Optimizer::foldPseudoAndOr(G4_BB* bb, INST_LIST_ITER& ii)
74287456
return;
74297457
}
74307458

7459+
// r0 copy is needed only if:
7460+
// a. pre-emption VISA option is enabled OR
7461+
// b. current object is kernel with stack calls since VISA ABI requires r0 copy to be available in a pre-defined register
7462+
if (!R0CopyNeeded())
7463+
return;
7464+
74317465
// Skip copying of ``copy of R0'' if it's never assigned, a case where
74327466
// ``copy of R0'' is never used. As EOT always use ``copy of R0'', that
74337467
// case only happens for synthetic tests where no practical code is

visa/Optimizer.h

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -196,6 +196,9 @@ class Optimizer
196196

197197
void accSubPostSchedule();
198198

199+
// return true if BuiltInR0 gets a different allocation than r0
200+
bool R0CopyNeeded();
201+
199202
private:
200203
/* below member functions are used for message header opt */
201204
bool isHeaderOptCandidate(G4_INST *, G4_INST *);

visa/PhyRegUsage.cpp

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1287,7 +1287,6 @@ void getForbiddenGRFs(
12871287
if (kernel.getKernelType() != VISA_3D ||
12881288
kernel.getOption(vISA_enablePreemption) ||
12891289
reserveSpillSize > 0 ||
1290-
stackCallRegSize > 0 ||
12911290
kernel.getOption(vISA_ReserveR0))
12921291
{
12931292
regNum.push_back(0);

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