@@ -23,16 +23,18 @@ void GenXVerify::verifyRegioning(const CallInst &CI,
2323 auto ensureNumEls4_8_16_and_offsetIsAMultipleOf =
2424 [&](const auto NumElts, const Twine NumEltsArgDesc,
2525 unsigned OffsetOpndNum) -> void {
26- if (InvariantSet <= GenXVerifyInvariantSet::PreGenXLegalization)
26+ if (InvariantSet < GenXVerifyInvariantSet::PostGenXLegalization)
27+ return ;
28+ if (!ensure (NumElts == 4 || NumElts == 8 || NumElts == 16 ,
29+ NumEltsArgDesc + " must be 4, 8 or 16"
2730 return ;
28- ensure (NumElts == 4 || NumElts == 8 || NumElts == 16 ,
29- NumEltsArgDesc + " must be 4, 8 or 16"
3031 const auto *OffsetInElementsConstInt =
3132 llvm::dyn_cast<llvm::ConstantInt>(CI.getOperand (OffsetOpndNum));
32- ensure (OffsetInElementsConstInt,
33- " OffsetInElements must be a constant integer"
33+ if (!ensure (OffsetInElementsConstInt,
34+ " offset in elements must be a constant integer"
35+ return ;
3436 ensure (!(OffsetInElementsConstInt->getZExtValue () % NumElts),
35- " OffsetInElements must be multiple of the number of elements of "
37+ " offset in elements must be multiple of the number of elements of "
3638 NumEltsArgDesc,
3739 CI);
3840 };
@@ -58,30 +60,50 @@ void GenXVerify::verifyRegioning(const CallInst &CI,
5860 if (!ensure (IGCLLVM::getNumArgOperands (&CI) == 2 ,
5961 " rdpredregion* intrinsics must have 2 operands"
6062 return ;
61- const auto *RetT = dyn_cast<IGCLLVM::FixedVectorType>(
63+ const auto *RetVT = dyn_cast<IGCLLVM::FixedVectorType>(
6264 CI.getCalledFunction ()->getReturnType ());
63- ensure (RetT, " return type must be a vector"
64- ensureNumEls4_8_16_and_offsetIsAMultipleOf (RetT->getNumElements (),
65+ if (!ensure (RetVT, " return type must be a vector"
66+ return ;
67+ ensureNumEls4_8_16_and_offsetIsAMultipleOf (RetVT->getNumElements (),
6568 " returned vector" 1 );
6669 }
6770 return ;
68- case GenXIntrinsic::genx_wrpredpredregion:
71+ case GenXIntrinsic::genx_wrpredpredregion: {
6972 if (!ensure (IGCLLVM::getNumArgOperands (&CI) == 4 ,
7073 " wrpredpredregion* intrinsics must have 4 operands"
7174 return ;
75+
76+ // The constant offset indexes both the vector itself and the predicate.
77+ // This intrinsic is valid only if the predicate is an EM value, and the
78+ // subvector operand is the result of a cmp (which is then baled in).
7279 ensure (isa<CmpInst>(CI.getOperand (1 )),
7380 " subvector to write must be the direct result of a cmp instruction"
7481 CI);
82+
83+ const auto *SubvectorToWriteT =
84+ dyn_cast<IGCLLVM::FixedVectorType>(CI.getOperand (1 )->getType ());
85+
86+ if (!ensure (SubvectorToWriteT, " subvector to write must be a fixed vector"
87+ CI))
88+ return ;
89+ ensureNumEls4_8_16_and_offsetIsAMultipleOf (
90+ SubvectorToWriteT->getNumElements (), " subvector to write" 2 );
91+
7592 // TODO: This intrinsic is valid only if the predicate is an EM value
7693 // CI.getOperand(3)
77- LLVM_FALLTHROUGH;
94+ }
95+ return ;
7896 case GenXIntrinsic::genx_wrpredregion: {
7997 if (!ensure (IGCLLVM::getNumArgOperands (&CI) == 3 ,
8098 " wrpredregion* intrinsics must have 3 operands"
8199 return ;
100+
82101 const auto *SubvectorToWriteT =
83102 dyn_cast<IGCLLVM::FixedVectorType>(CI.getOperand (1 )->getType ());
84- ensure (SubvectorToWriteT, " subvector to write must be a fixed vector"
103+
104+ if (!ensure (SubvectorToWriteT, " subvector to write must be a fixed vector"
105+ CI))
106+ return ;
85107 ensureNumEls4_8_16_and_offsetIsAMultipleOf (
86108 SubvectorToWriteT->getNumElements (), " subvector to write" 2 );
87109 }
@@ -134,15 +156,14 @@ void GenXVerify::verifyRegioning(const CallInst &CI,
134156
135157 const llvm::Value *WidthOpnd = CI.getOperand (SrcOpndIdx + 2 );
136158 const auto WidthConstantInt = dyn_cast<llvm::ConstantInt>(WidthOpnd);
137- ensure (WidthConstantInt, " width must be a constant int"
138159
139- const unsigned Width =
140- WidthConstantInt ? WidthConstantInt-> getZExtValue ()
141- : 1 /* a value making following checks happy (for
142- non-failing LIT tests runs). If width was not a
143- constant, we have already reported above. */
144- ;
145- ensure (Width, " the width must be non-zero. " , CI) ;
160+ if (! ensure (WidthConstantInt, " width must be a constant int " , CI))
161+ return ;
162+
163+ const unsigned Width = WidthConstantInt-> getZExtValue ();
164+
165+ if (! ensure (Width, " the width must be non-zero. " , CI))
166+ return ;
146167
147168 const unsigned TotalElCount_ExecSize =
148169 GenXIntrinsic::isRdRegion (IntrinsicId)
@@ -198,6 +219,12 @@ void GenXVerify::verifyRegioning(const CallInst &CI,
198219 const auto *DstSrcOpndT = DstSrcOpnd->getType ();
199220 const auto *DstSrcOpndMaybeVT =
200221 dyn_cast<IGCLLVM::FixedVectorType>(DstSrcOpndT);
222+
223+ // TODO:spec review: some IRs have arg0 as a scalar with undef value.
224+ ensure (DstSrcOpndMaybeVT,
225+ " destination-source (arg0) must be a fixed vector."
226+ IsFatal::No);
227+
201228 // TODO:spec review: some IRs have arg0 as a scalar with undef value.
202229 ensure (DstSrcOpndMaybeVT,
203230 " source-destination (arg0) operand must be a fixed vector."
@@ -207,26 +234,22 @@ void GenXVerify::verifyRegioning(const CallInst &CI,
207234 " The arg1 subvector must have the same element type as the arg0 vector"
208235 CI);
209236
210- if (InvariantSet > GenXVerifyInvariantSet::PreIrAdaptors) {
211- // TODO:spec review: some IRs have arg0 as a scalar with undef value.
237+ if (InvariantSet >= GenXVerifyInvariantSet::PostIrAdaptors) {
212238 if (SrcOpndMaybeVT && DstSrcOpndMaybeVT)
213239 ensure (SrcOpndMaybeVT->getNumElements () <=
214240 DstSrcOpndMaybeVT->getNumElements (),
215- " The arg1 subvector must be no lardger than arg0 vector"
216- }
241+ " The arg1 subvector must be no larger than arg0 vector"
217242
218- // After lowering, the arg1 subvector to write can be a scalar of the
219- // same type as an element of arg0, indicating that the region has one
220- // element. (Lowering lowers an insertelement to this type of wrregion.)
221- if (InvariantSet > GenXVerifyInvariantSet::PreIrAdaptors) {
222- ensure (SrcOpndMaybeVT || (!SrcOpndMaybeVT && Width == 1 ),
223- " subregion to write may be a scalar if the number of elements in "
243+ // After lowering, the arg1 subvector to write can be a scalar of the
244+ // same type as an element of arg0, indicating that the region has one
245+ // element. (Lowering lowers an insertelement to this type of wrregion.)
246+ ensure (SrcOpndMaybeVT ||
247+ (InvariantSet >= GenXVerifyInvariantSet::PostGenXLowering &&
248+ Width == 1 ),
249+ " after genx lowering subregion to write may be a scalar if the "
250+ " number of elements in "
224251 " subregion is 1."
225252 CI);
226- // TODO:spec review: some IRs have arg0 as a scalar with undef value.
227- ensure (DstSrcOpndMaybeVT,
228- " destination-source (arg0) must be a fixed vector."
229- IsFatal::No);
230253 }
231254
232255 ensure (SrcOpndMaybeVT || SrcOpndT->getScalarType (),
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