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| 1 | +;=========================== begin_copyright_notice ============================ |
| 2 | +; |
| 3 | +; Copyright (C) 2024 Intel Corporation |
| 4 | +; |
| 5 | +; SPDX-License-Identifier: MIT |
| 6 | +; |
| 7 | +;============================ end_copyright_notice ============================= |
| 8 | + |
| 9 | +; REQUIRES: llvm-14-plus |
| 10 | +; RUN: igc_opt --opaque-pointers %s -S -o - --dx12 --inputcs --igc-constant-coalescing -dce | FileCheck %s |
| 11 | + |
| 12 | +define void @test_ldraw_merge() { |
| 13 | +entry: |
| 14 | + %a = call i16 @llvm.genx.GenISA.DCL.SystemValue.i16(i32 7) |
| 15 | + %src = sext i16 %a to i32 |
| 16 | + %0 = inttoptr i32 %src to ptr addrspace(2555909) |
| 17 | + %1 = call fast float @llvm.genx.GenISA.ldraw.indexed.f32.p2555909(ptr addrspace(2555909) %0, i32 %src, i32 4, i1 false) |
| 18 | + %2 = add i32 %src, 4 |
| 19 | + %3 = call fast float @llvm.genx.GenISA.ldraw.indexed.f32.p2555909(ptr addrspace(2555909) %0, i32 %2, i32 4, i1 false) |
| 20 | +; CHECK: %2 = call <2 x float> @llvm.genx.GenISA.ldrawvector.indexed.v2f32.p2555909(ptr addrspace(2555909) %0, i32 %1, i32 4, i1 false) |
| 21 | + call void @use.f32(float %1) |
| 22 | + call void @use.f32(float %3) |
| 23 | + ret void |
| 24 | +} |
| 25 | + |
| 26 | +declare void @use.f32(float) |
| 27 | + |
| 28 | +declare i16 @llvm.genx.GenISA.DCL.SystemValue.i16(i32) |
| 29 | + |
| 30 | +; Function Attrs: argmemonly nounwind readonly |
| 31 | +declare float @llvm.genx.GenISA.ldraw.indexed.f32.p2555909(ptr addrspace(2555909), i32, i32, i1) #0 |
| 32 | + |
| 33 | +attributes #0 = { argmemonly nounwind readonly } |
| 34 | + |
| 35 | +!igc.functions = !{!0} |
| 36 | + |
| 37 | +!0 = !{ptr @test_ldraw_merge, !1} |
| 38 | +!1 = !{!2, !3} |
| 39 | +!2 = !{!"function_type", i32 0} |
| 40 | +!3 = !{!"implicit_arg_desc"} |
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