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mshelegoigcbot
mshelego
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igcbot
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Change default float controls
Switch default denormals handling from flush-to-zero into retain.
1 parent 895ebe6 commit 83f5c59

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4 files changed

+39
-26
lines changed

4 files changed

+39
-26
lines changed

‎IGC/VectorCompiler/lib/GenXCodeGen/GenXFloatControl.cpp

Lines changed: 4 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -66,8 +66,10 @@ bool GenXFloatControl::runOnFunction(Function &F) {
6666
CRBits::SinglePrecisionDenorm | CRBits::HalfPrecisionDenorm;
6767
// Default float control:
6868
// rounding mode = nearest even
69-
// denormals = flush
70-
uint32_t FloatControl = CRBits::RTNE;
69+
// denormals = retain
70+
uint32_t FloatControl = CRBits::RTNE | CRBits::DoublePrecisionDenorm |
71+
CRBits::SinglePrecisionDenorm |
72+
CRBits::HalfPrecisionDenorm;
7173
const auto *Subtarget = &getAnalysis<TargetPassConfig>()
7274
.getTM<GenXTargetMachine>()
7375
.getGenXSubtarget();

‎IGC/VectorCompiler/test/GenXFloatControl/float_control.ll

Lines changed: 11 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -15,10 +15,19 @@
1515
; RUN: FileCheck %s --check-prefix=CHECK-VISA
1616

1717
; CHECK-LABEL: define dllexport spir_kernel void @kernel
18-
; CHECK-NOT: predef
18+
; CHECK-NEXT: [[AND_READ_PREDEF:[^ ]+]] = call <4 x i32> @llvm.genx.read.predef.reg.v4i32.v4i32(i32 14, <4 x i32> undef)
19+
; CHECK-NEXT: [[AND_RDREGION:[^ ]+]] = call i32 @llvm.genx.rdregioni.i32.v4i32.i16(<4 x i32> [[AND_READ_PREDEF]], i32 0, i32 1, i32 1, i16 0, i32 undef)
20+
; CHECK-NEXT: [[AND:[^ ]+]] = and i32 [[AND_RDREGION]], -1265
21+
; CHECK-NEXT: [[AND_WRREGION:[^ ]+]] = call <4 x i32> @llvm.genx.wrregioni.v4i32.i32.i16.i1(<4 x i32> [[AND_READ_PREDEF]], i32 [[AND]], i32 0, i32 1, i32 1, i16 0, i32 undef, i1 true)
22+
; CHECK-NEXT: call <4 x i32> @llvm.genx.write.predef.reg.v4i32.v4i32(i32 14, <4 x i32> [[AND_WRREGION]])
23+
; CHECK-NEXT: [[OR_READ_PREDEF:[^ ]+]] = call <4 x i32> @llvm.genx.read.predef.reg.v4i32.v4i32(i32 14, <4 x i32> undef)
24+
; CHECK-NEXT: [[OR_RDREGION:[^ ]+]] = call i32 @llvm.genx.rdregioni.i32.v4i32.i16(<4 x i32> [[OR_READ_PREDEF]], i32 0, i32 1, i32 1, i16 0, i32 undef)
25+
; CHECK-NEXT: [[OR:[^ ]+]] = or i32 [[OR_RDREGION]], 1216
26+
; CHECK-NEXT: [[OR_WRREGION:[^ ]+]] = call <4 x i32> @llvm.genx.wrregioni.v4i32.i32.i16.i1(<4 x i32> [[OR_READ_PREDEF]], i32 [[OR]], i32 0, i32 1, i32 1, i16 0, i32 undef, i1 true)
1927
; CHECK: ret
2028
; CHECK-VISA-LABEL: .function "kernel_BB_0"
21-
; CHECK-VISA-NOT: %cr0
29+
; CHECK-VISA: and (M1, 1) %cr0(0,0)<1> %cr0(0,0)<0;1,0> 0xfffffb0f:d
30+
; CHECK-VISA-NEXT: or (M1, 1) %cr0(0,0)<1> %cr0(0,0)<0;1,0> 0x4c0:d
2231
; CHECK-VISA: ret (M1, 1)
2332
define dllexport spir_kernel void @kernel(i32 %a, i64 %privBase) #0 {
2433
call spir_func i32 @stackcall(i32 %a) #1

‎IGC/VectorCompiler/test/VisaRegAlloc/no_coalescing.ll

Lines changed: 16 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
;=========================== begin_copyright_notice ============================
22
;
3-
; Copyright (C) 2021 Intel Corporation
3+
; Copyright (C) 2021-2024 Intel Corporation
44
;
55
; SPDX-License-Identifier: MIT
66
;
@@ -13,17 +13,15 @@
1313
; RUN: -vc-fg-dump-prefix=%basename_t_ \
1414
; RUN: -finalizer-opts='-generateDebugInfo' -o /dev/null
1515

16-
; COM: These checks are brittle and differ between LLVM versions.
17-
; COM: Currently accounted for with {{(<pre-llvm11-val>|<llvm11-val>)}} regexp syntax.
18-
; FIXME: Return unconditional checks once LLVM version is unified for IGC.
19-
2016
; RUN: FileCheck %s --input-file=%basename_t_M_.regalloc --check-prefix=CHECK_NOCOALESC
21-
; CHECK_NOCOALESC: [t7] (4 bytes, length 13) arg1:[0,13)
22-
; CHECK_NOCOALESC-NEXT: [t6] (4 bytes, length 7) arg:[0,7)
23-
; CHECK_NOCOALESC-NEXT: [v32] (64 bytes, length {{(4|6)}}) :[5,{{(9|11)}})
24-
; CHECK_NOCOALESC-NEXT: [v33] (64 bytes, length {{(4|2)}}) :[7,{{(11|9)}})
25-
; CHECK_NOCOALESC-NEXT: [v34] (64 bytes, length 2) :[9,11)
26-
; CHECK_NOCOALESC-NEXt: [v35] (64 bytes, length 2) :[11,13)
17+
; CHECK_NOCOALESC: [t7] (4 bytes, length 33) arg1:[0,33)
18+
; CHECK_NOCOALESC-NEXT: [t6] (4 bytes, length 27) arg:[0,27)
19+
; CHECK_NOCOALESC-NEXT: [v34] (64 bytes, length 6) :[25,31)
20+
; CHECK_NOCOALESC-NEXT: [v32] (16 bytes, length 3) :[10,13)
21+
; CHECK_NOCOALESC-NEXT: [v33] (16 bytes, length 3) :[20,23)
22+
; CHECK_NOCOALESC-NEXT: [v35] (64 bytes, length 2) :[27,29)
23+
; CHECK_NOCOALESC-NEXT: [v36] (64 bytes, length 2) :[29,31)
24+
; CHECK_NOCOALESC-NEXT: [v37] (64 bytes, length 2) :[31,33)
2725
; CHECK_NOCOALESC: Register pressure (bytes):
2826
; CHECK_NOCOALESC: Flag pressure (bytes):
2927

@@ -34,11 +32,13 @@
3432
; RUN: -finalizer-opts='-generateDebugInfo' -o /dev/null
3533

3634
; RUN: FileCheck %s --input-file=%basename_t_M_.regalloc --check-prefix=CHECK_COALESC
37-
; CHECK_COALESC: [t7] (4 bytes, length 13) arg1:[0,13)
38-
; CHECK_COALESC-NEXT: [t6] (4 bytes, length 7) arg:[0,7)
39-
; CHECK_COALESC-NEXT: [v{{(33|32)}}] (64 bytes, length 6) :[5,11)
40-
; CHECK_COALESC-NEXT: [v{{(32|33)}}] (64 bytes, length 4) :[7,11)
41-
; CHECK_COALESC-NEXt: [v34] (64 bytes, length 2) :[11,13)
35+
; CHECK_COALESC: [t7] (4 bytes, length 33) arg1:[0,33)
36+
; CHECK_COALESC-NEXT: [t6] (4 bytes, length 27) arg:[0,27)
37+
; CHECK_COALESC-NEXT: [v34] (64 bytes, length 6) :[25,31)
38+
; CHECK_COALESC-NEXT: [v35] (64 bytes, length 4) :[27,31)
39+
; CHECK_COALESC-NEXT: [v32] (16 bytes, length 3) :[10,13)
40+
; CHECK_COALESC-NEXT: [v33] (16 bytes, length 3) :[20,23)
41+
; CHECK_COALESC-NEXT: [v36] (64 bytes, length 2) :[31,33)
4242
; CHECK_COALESC: Register pressure (bytes):
4343
; CHECK_COALESC: Flag pressure (bytes):
4444

‎IGC/VectorCompiler/test/VisaRegAlloc/reg_alloc_dump_basic.ll

Lines changed: 8 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
;=========================== begin_copyright_notice ============================
22
;
3-
; Copyright (C) 2021 Intel Corporation
3+
; Copyright (C) 2021-2024 Intel Corporation
44
;
55
; SPDX-License-Identifier: MIT
66
;
@@ -15,11 +15,13 @@
1515
; COM: these checks are potentially brittle. Though, the size of the test is
1616
; COM: small and it should be easy to modify if problem arise
1717
; RUN: FileCheck %s --input-file=%basename_t_M_.regalloc
18-
; CHECK: [t7] (4 bytes, length 11) arg1:[0,11)
19-
; CHECK-NEXT: [t6] (4 bytes, length 7) arg:[0,7)
20-
; CHECK-NEXT: [v32] (64 bytes, length 4) :[5,9)
21-
; CHECK-NEXT: [v33] (64 bytes, length 2) :[7,9)
22-
; CHECK-NEXT: [v34] (64 bytes, length 2) :[9,11)
18+
; CHECK: [t7] (4 bytes, length 31) arg1:[0,31)
19+
; CHECK-NEXT: [t6] (4 bytes, length 27) arg:[0,27)
20+
; CHECK-NEXT: [v34] (64 bytes, length 4) :[25,29)
21+
; CHECK-NEXT: [v32] (16 bytes, length 3) :[10,13)
22+
; CHECK-NEXT: [v33] (16 bytes, length 3) :[20,23)
23+
; CHECK-NEXT: [v35] (64 bytes, length 2) :[27,29)
24+
; CHECK-NEXT: [v36] (64 bytes, length 2) :[29,31)
2325
; CHECK: Register pressure (bytes):
2426
; CHECK: Flag pressure (bytes):
2527

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