vISA scheduler minor code change.

vISA scheduler minor code change.

Author: petechou

visa/LocalScheduler/LatencyTable.cpp

@@ -32,9 +32,9 @@ class LatencyTableLegacy : public LatencyTable {
 template <PlatformGen Gen>
 class LatencyTableXe: public LatencyTable {
   // Select latency information based on platform generation.
-  using LI = typename std::conditional<Gen >= PlatformGen::XE,
-                                       XELatencyInfo,
-                                       void>::type;
+  using LI2 = void;
+  using LI = typename std::conditional<Gen == PlatformGen::XE,
+                                       XELatencyInfo, LI2>::type;
 public:
   LatencyTableXe(const IR_Builder& builder) : LatencyTable(builder) {
     static_assert(Gen >= PlatformGen::XE);
@@ -50,11 +50,14 @@ class LatencyTableXe: public LatencyTable {
   uint16_t getDPASLatency(uint8_t repeatCount) const override;
 private:
   uint16_t getMsgLatency(const G4_INST *Inst) const;
+  uint16_t getSamplerLatency() const;
+  uint16_t getDPL3Latency() const;
+  uint16_t getLSCL3Latency(bool typed) const;
   uint16_t getMathLatency(const G4_INST *inst) const;
-  uint16_t getBranchLatency(const G4_INST *inst) const;
+  uint16_t getBranchLatency() const;
   uint16_t getIntrinsicLatency(const G4_INST *inst) const;
   uint16_t getDPASLatency(const G4_InstDpas *dpas) const;
-  uint16_t getARFAccessLatency(const G4_INST *inst) const;
+  uint16_t getARFAccessLatency() const;
   uint16_t getArithmeticLatency(const G4_INST *inst) const;
 };
 
@@ -161,14 +164,14 @@ uint16_t LatencyTableXe<Gen>::getLatency(const G4_INST *Inst) const {
   if (Inst->isMath())
     return getMathLatency(Inst);
   if (Inst->isFlowControl())
-    return getBranchLatency(Inst);
+    return getBranchLatency();
   if (Inst->isIntrinsic())
     return getIntrinsicLatency(Inst);
   if (Inst->isDpas())
     return getDPASLatency(Inst->asDpasInst());
   if (Inst->writesFlag() ||
       (Inst->getDst() && Inst->getDst()->isDirectA0()))
-    return getARFAccessLatency(Inst);
+    return getARFAccessLatency();
   if (Inst->isArithmetic())
     return getArithmeticLatency(Inst);
 
@@ -194,36 +197,50 @@ uint16_t LatencyTableXe<Gen>::getMsgLatency(const G4_INST *Inst) const {
       bool isCachedInL1 = MsgDesc->getCachingL1() == Caching::CA ||
                           (MsgDesc->getCachingL1() != Caching::UC &&
                            m_builder.getOption(vISA_assumeL1Hit));
-      if (MsgDesc->isTyped()) {
-        return isCachedInL1 ? value_of(LI::LSC_TYPED_L1)
-                            : value_of(LI::LSC_TYPED_L3);
+      bool typed = MsgDesc->isTyped();
+      if (isCachedInL1) {
+        return typed ? value_of(LI::LSC_TYPED_L1)
+                     : value_of(LI::LSC_UNTYPED_L1);
       } else {
-        return isCachedInL1 ? value_of(LI::LSC_UNTYPED_L1)
-                            : value_of(LI::LSC_UNTYPED_L3);
+        return getLSCL3Latency(typed);
       }
     }
   }
   if (MsgDesc->isSLM())
     return Inst->asSendInst()->isFence() ? value_of(LI::SLM_FENCE)
                                          : value_of(LI::SLM16);
   if (MsgDesc->isSampler())
-    return value_of(LI::SAMPLER_L3);
+    return getSamplerLatency();
   if (MsgDesc->isHDC())
-    return value_of(LI::DP_L3);
+    return getDPL3Latency();
   if (MsgDesc->isBarrier())
     return value_of(LI::BARRIER);
   return value_of(LI::SEND_OTHERS);
 }
 
+template<PlatformGen Gen>
+uint16_t LatencyTableXe<Gen>::getSamplerLatency() const {
+  return value_of(LI::SAMPLER_L3);
+}
+
+template<PlatformGen Gen>
+uint16_t LatencyTableXe<Gen>::getLSCL3Latency(bool typed) const {
+  return value_of(typed ? LI::LSC_TYPED_L3 : LI::LSC_UNTYPED_L3);
+}
+
+template<PlatformGen Gen>
+uint16_t LatencyTableXe<Gen>::getDPL3Latency() const {
+  return value_of(LI::DP_L3);
+}
+
 template<PlatformGen Gen>
 uint16_t LatencyTableXe<Gen>::getMathLatency(const G4_INST *Inst) const {
   vASSERT(Inst->isMath());
   return value_of(LI::MATH);
 }
 
 template<PlatformGen Gen>
-uint16_t LatencyTableXe<Gen>::getBranchLatency(const G4_INST *Inst) const {
-  vASSERT(Inst->isFlowControl());
+uint16_t LatencyTableXe<Gen>::getBranchLatency() const {
   return value_of(LI::BRANCH);
 }
 
@@ -239,9 +256,7 @@ uint16_t LatencyTableXe<Gen>::getDPASLatency(const G4_InstDpas *dpas) const {
 }
 
 template<PlatformGen Gen>
-uint16_t LatencyTableXe<Gen>::getARFAccessLatency(const G4_INST *Inst) const {
-  vASSERT(Inst->writesFlag() ||
-          (Inst->getDst() && Inst->getDst()->isDirectA0()));
+uint16_t LatencyTableXe<Gen>::getARFAccessLatency() const {
   return value_of(LI::ARF);
 }
 
@@ -293,8 +308,8 @@ LatencyTableXe<PlatformGen::XE>::getDPASLatency(uint8_t repeatCount) const {
   case Xe_PVCXT:
     return value_of(LI::DPAS) + repeatCount;
   default: // Not supported platform
-    // TODO: Add vISA_ASSERT_UNREACHABLE.
-    return 46;
+    vISA_ASSERT_UNREACHABLE("Unsupported platform");
+    return value_of(LI::UNKNOWN);
   }
 }
 template<>

visa/LocalScheduler/SWSB_G4IR.h

@@ -957,7 +957,7 @@ class SWSB {
   const unsigned tokenAfterWriteSendSlmCycle;
   const unsigned tokenAfterWriteSendMemoryCycle;
   const unsigned tokenAfterWriteSendSamplerCycle;
-  int tokenAfterDPASCycle;
+  int tokenAfterDPASCycle = 0;
 
   // For profiling
   uint32_t syncInstCount = 0;
@@ -1156,8 +1156,10 @@ class SWSB {
     indexes.longIndex = 0;
     indexes.DPASIndex = 0;
     indexes.mathIndex = 0;
-    tokenAfterDPASCycle =
-        LatencyTable::createLatencyTable(*k.fg.builder)->getDPASLatency(8);
+    if (k.fg.builder->hasDPAS()) {
+      tokenAfterDPASCycle =
+          LatencyTable::createLatencyTable(*k.fg.builder)->getDPASLatency(8);
+    }
   }
   ~SWSB() {}
   void SWSBGenerator();