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fangliu2020igcbot
fangliu2020
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Changes in code.
1 parent df8a499 commit 9b84c10

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3 files changed

+39
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‎visa/LocalScheduler/LocalScheduler_G4IR.cpp

Lines changed: 16 additions & 56 deletions
Original file line numberDiff line numberDiff line change
@@ -38,9 +38,6 @@ void LocalScheduler::localScheduling() {
3838
const Options *m_options = fg.builder->getOptions();
3939
LatencyTable LT(fg.builder);
4040

41-
PointsToAnalysis p(fg.getKernel()->Declares, fg.size());
42-
p.doPointsToAnalysis(fg);
43-
4441
uint32_t totalCycles = 0;
4542
uint32_t scheduleStartBBId =
4643
m_options->getuInt32Option(vISA_LocalSchedulingStartBB);
@@ -86,7 +83,7 @@ void LocalScheduler::localScheduling() {
8683
G4_BB *tempBB = fg.createNewBB(false);
8784
sections.push_back(tempBB);
8885
tempBB->splice(tempBB->begin(), (*ib), (*ib)->begin(), inst_it);
89-
G4_BB_Schedule schedule(fg.getKernel(), bbMem, tempBB, LT, p);
86+
G4_BB_Schedule schedule(fg.getKernel(), bbMem, tempBB, LT);
9087
sequentialCycles += schedule.sequentialCycle;
9188
sendStallCycles += schedule.sendStallCycle;
9289
count = 0;
@@ -108,7 +105,7 @@ void LocalScheduler::localScheduling() {
108105
bbInfo[i].loopNestLevel = (*ib)->getNestLevel();
109106
totalCycles += sequentialCycles;
110107
} else {
111-
G4_BB_Schedule schedule(fg.getKernel(), bbMem, *ib, LT, p);
108+
G4_BB_Schedule schedule(fg.getKernel(), bbMem, *ib, LT);
112109
bbInfo[i].id = (*ib)->getId();
113110
bbInfo[i].staticCycle = schedule.sequentialCycle;
114111
bbInfo[i].sendStallCycle = schedule.sendStallCycle;
@@ -198,14 +195,15 @@ void G4_BB_Schedule::dumpSchedule(G4_BB *bb) {
198195
// - creates a new instruction listing within a BBB
199196
//
200197
G4_BB_Schedule::G4_BB_Schedule(G4_Kernel *k, Mem_Manager &m, G4_BB *block,
201-
const LatencyTable &LT, PointsToAnalysis &p)
202-
: mem(m), bb(block), kernel(k), pointsToAnalysis(p)
198+
const LatencyTable &LT)
199+
: mem(m), bb(block), kernel(k)
200+
203201
{
204202
// we use local id in the scheduler for determining two instructions' original
205203
// ordering
206204
bb->resetLocalIds();
207205

208-
DDD ddd(mem, bb, LT, k, p);
206+
DDD ddd(mem, bb, LT, k);
209207
// Generate pairs of TypedWrites
210208
bool doMessageFuse =
211209
(k->fg.builder->fuseTypedWrites() && k->getSimdSize() >= g4::SIMD16) ||
@@ -332,44 +330,6 @@ static Mask getMaskForOp(G4_Operand *opnd, Gen4_Operand_Number opnd_num,
332330
return Mask(LB, RB, nonContiguousStride, opnd->getAccRegSel());
333331
}
334332

335-
void DDD::getBucketsForIndirectOperand(G4_INST *inst,
336-
Gen4_Operand_Number opnd_num,
337-
std::vector<BucketDescr> &BDvec) {
338-
G4_Declare *addrdcl = nullptr;
339-
G4_Operand *opnd = inst->getOperand(opnd_num);
340-
if (opnd) {
341-
addrdcl = GetTopDclFromRegRegion(opnd);
342-
}
343-
assert(addrdcl != nullptr && "address declare can not be nullptr");
344-
345-
auto pointsToSet = pointsToAnalysis.getAllInPointsTo(addrdcl->getRegVar());
346-
for (auto &pt : *pointsToSet) {
347-
uint32_t varID = pt.var->getId();
348-
G4_Declare *dcl = pt.var->getDeclare()->getRootDeclare();
349-
G4_RegVar *var = dcl->getRegVar();
350-
351-
assert(var->getId() == varID &&
352-
"RA verification error: Invalid regVar ID!");
353-
assert(var->getPhyReg()->isGreg() &&
354-
"RA verification error: Invalid dst reg!");
355-
356-
uint32_t regNum = var->getPhyReg()->asGreg()->getRegNum();
357-
uint32_t regOff = var->getPhyRegOff();
358-
int linearizedStart = regNum * kernel->numEltPerGRF<Type_UB>() +
359-
regOff * TypeSize(dcl->getElemType());
360-
int linearizedEnd = linearizedStart + dcl->getByteSize() - 1;
361-
362-
int startingBucket = linearizedStart / kernel->numEltPerGRF<Type_UB>();
363-
int endingBucket = linearizedEnd / kernel->numEltPerGRF<Type_UB>();
364-
Mask mask(linearizedStart, linearizedEnd, false, opnd->getAccRegSel());
365-
int numBuckets = endingBucket - startingBucket + 1;
366-
for (int j = startingBucket; j < (startingBucket + numBuckets); j++) {
367-
BDvec.push_back(BucketDescr(j, mask, opnd_num));
368-
}
369-
}
370-
return;
371-
}
372-
373333
void DDD::getBucketsForOperand(G4_INST *inst, Gen4_Operand_Number opnd_num,
374334
std::vector<BucketDescr> &BDvec) {
375335
G4_Operand *opnd = inst->getOperand(opnd_num);
@@ -476,7 +436,8 @@ static inline bool hasIndirection(G4_Operand *opnd,
476436
// return all bucket descriptors that the physical register can map
477437
// to. This requires taking in to account exec size, data
478438
// type, and whether inst is a send
479-
void DDD::getBucketDescrs(Node *node, std::vector<BucketDescr> &BDvec) {
439+
bool DDD::getBucketDescrs(Node *node, std::vector<BucketDescr> &BDvec) {
440+
bool hasIndir = false;
480441
for (G4_INST *inst : node->instVec) {
481442
// Iterate over all operands and create buckets.
482443
for (Gen4_Operand_Number opndNum :
@@ -489,9 +450,7 @@ void DDD::getBucketDescrs(Node *node, std::vector<BucketDescr> &BDvec) {
489450
}
490451
getBucketsForOperand(inst, opndNum, BDvec);
491452
// Check if this operand is an indirect access
492-
if (hasIndirection(opnd, opndNum)) {
493-
getBucketsForIndirectOperand(inst, opndNum, BDvec);
494-
}
453+
hasIndir |= hasIndirection(opnd, opndNum);
495454
}
496455

497456
// Sends need an additional bucket
@@ -504,7 +463,7 @@ void DDD::getBucketDescrs(Node *node, std::vector<BucketDescr> &BDvec) {
504463
}
505464
}
506465

507-
return;
466+
return hasIndir;
508467
}
509468

510469
// This class hides the internals of dependence tracking using buckets
@@ -1235,9 +1194,8 @@ bool DDD::hasSameSourceOneDPAS(G4_INST *curInst, G4_INST *nextInst,
12351194
// dependencies with all insts in live set. After analyzing
12361195
// dependencies and creating necessary edges, current inst
12371196
// is inserted in all buckets it touches.
1238-
DDD::DDD(Mem_Manager &m, G4_BB *bb, const LatencyTable &lt, G4_Kernel *k,
1239-
PointsToAnalysis &p)
1240-
: mem(m), LT(lt), kernel(k), pointsToAnalysis(p) {
1197+
DDD::DDD(Mem_Manager &m, G4_BB *bb, const LatencyTable &lt, G4_Kernel *k)
1198+
: mem(m), LT(lt), kernel(k) {
12411199
Node *lastBarrier = nullptr;
12421200
HWthreadsPerEU = k->getNumThreads();
12431201
useMTLatencies = getBuilder()->useMultiThreadLatency();
@@ -1275,6 +1233,7 @@ DDD::DDD(Mem_Manager &m, G4_BB *bb, const LatencyTable &lt, G4_Kernel *k,
12751233
node = new (mem) Node(nodeId, *iInst, depEdgeAllocator, LT);
12761234
allNodes.push_back(node);
12771235
G4_INST *curInst = node->getInstructions()->front();
1236+
bool hasIndir = false;
12781237
BDvec.clear();
12791238

12801239
if (curInst->getNumSrc() == 3) {
@@ -1352,8 +1311,9 @@ DDD::DDD(Mem_Manager &m, G4_BB *bb, const LatencyTable &lt, G4_Kernel *k,
13521311
}
13531312
}
13541313
// Get buckets for all physical registers assigned in curInst
1355-
getBucketDescrs(node, BDvec);
1356-
if (curInst->isSend() && curInst->asSendInst()->isFence()) {
1314+
hasIndir = getBucketDescrs(node, BDvec);
1315+
if (hasIndir || (curInst->isSend() && curInst->asSendInst()->isFence())) {
1316+
// If inst has indirect src/dst then treat it as a barrier.
13571317
node->MarkAsUnresolvedIndirAddressBarrier();
13581318
}
13591319

‎visa/LocalScheduler/LocalScheduler_G4IR.h

Lines changed: 3 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -14,7 +14,6 @@ SPDX-License-Identifier: MIT
1414
#include "../FlowGraph.h"
1515
#include "../G4_IR.hpp"
1616
#include "../Mem_Manager.h"
17-
#include "../RegAlloc.h"
1817
#include "../Timer.h"
1918
#include "Dependencies_G4IR.h"
2019
#include "LatencyTable.h"
@@ -245,7 +244,6 @@ class DDD {
245244
int TOTAL_BUCKETS;
246245
int totalGRFNum;
247246
G4_Kernel *kernel;
248-
PointsToAnalysis &pointsToAnalysis;
249247

250248
// Gather all initial ready nodes.
251249
void collectRoots();
@@ -269,8 +267,7 @@ class DDD {
269267
const G4_INST &nextInst) const;
270268

271269
public:
272-
DDD(Mem_Manager &m, G4_BB *bb, const LatencyTable &lt, G4_Kernel *k,
273-
PointsToAnalysis &p);
270+
DDD(Mem_Manager &m, G4_BB *bb, const LatencyTable &lt, G4_Kernel *k);
274271
~DDD() {
275272
if (Nodes.size()) {
276273
for (NODE_LIST_ITER nIter = Nodes.begin(); nIter != Nodes.end();
@@ -294,11 +291,8 @@ class DDD {
294291

295292
void getBucketsForOperand(G4_INST *inst, Gen4_Operand_Number opnd_num,
296293
std::vector<BucketDescr> &buckets);
297-
void getBucketsForIndirectOperand(G4_INST *inst,
298-
Gen4_Operand_Number opnd_num,
299-
std::vector<BucketDescr> &BDvec);
300294
// Returns true if instruction has any indirect operands (dst or src)
301-
void getBucketDescrs(Node *inst, std::vector<BucketDescr> &bucketDescrs);
295+
bool getBucketDescrs(Node *inst, std::vector<BucketDescr> &bucketDescrs);
302296

303297
uint32_t getEdgeLatency_old(Node *node, DepType depT);
304298
uint32_t getEdgeLatency(Node *node, DepType depT);
@@ -314,7 +308,6 @@ class G4_BB_Schedule {
314308
G4_BB *bb;
315309
DDD *ddd;
316310
G4_Kernel *kernel;
317-
PointsToAnalysis &pointsToAnalysis;
318311

319312
public:
320313
std::vector<Node *> scheduledNodes;
@@ -324,7 +317,7 @@ class G4_BB_Schedule {
324317

325318
// Constructor
326319
G4_BB_Schedule(G4_Kernel *kernel, Mem_Manager &m, G4_BB *bb,
327-
const LatencyTable &LT, PointsToAnalysis &p);
320+
const LatencyTable &LT);
328321
void *operator new(size_t sz, Mem_Manager &m) { return m.alloc(sz); }
329322
// Dumps the schedule
330323
void emit(std::ostream &);

‎visa/PhyRegCompute.cpp

Lines changed: 20 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -34,13 +34,18 @@ void G4_SrcRegRegion::computePReg(const IR_Builder &builder) {
3434

3535
dcl->setGRFBaseOffset(linearizedStart);
3636
}
37+
#if 0
38+
if (baseVar->getPhyReg()->isA0())
39+
{
40+
G4_Declare* dcl = baseVar->getDeclare();
3741

38-
if (baseVar->getPhyReg()->isA0()) {
39-
G4_Declare *dcl = baseVar->getDeclare();
40-
subRegNum = baseVar->getPhyRegOff();
41-
unsigned int linearizedStart = subRegNum * TypeSize(ADDR_REG_TYPE);
42-
dcl->setGRFBaseOffset(linearizedStart);
43-
}
42+
subRegNum = baseVar->getPhyRegOff();
43+
44+
unsigned int linearizedStart = subRegNum * TypeSize(ADDR_REG_TYPE);
45+
46+
dcl->setGRFBaseOffset(linearizedStart);
47+
}
48+
#endif
4449
}
4550
}
4651

@@ -68,14 +73,17 @@ void G4_DstRegRegion::computePReg(const IR_Builder &builder) {
6873
dcl->setGRFBaseOffset(linearizedStart);
6974
}
7075

71-
if (baseVar->getPhyReg()->isA0()) {
72-
G4_Declare *dcl = baseVar->getDeclare();
76+
#if 0
77+
if (baseVar->getPhyReg()->isA0())
78+
{
79+
G4_Declare* dcl = baseVar->getDeclare();
7380

74-
subRegNum = baseVar->getPhyRegOff();
81+
subRegNum = baseVar->getPhyRegOff();
7582

76-
unsigned int linearizedStart = subRegNum * TypeSize(ADDR_REG_TYPE);
83+
unsigned int linearizedStart = subRegNum * TypeSize(ADDR_REG_TYPE);
7784

78-
dcl->setGRFBaseOffset(linearizedStart);
79-
}
85+
dcl->setGRFBaseOffset(linearizedStart);
86+
}
87+
#endif
8088
}
8189
}

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