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YuriPlyakhinigcbot
YuriPlyakhin
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Get rid of unnecessary TF32 to Float conversion
Remove unnecessary TFloat32 to Float conversion, since TFloat32 is already valid Float Update F -> TF32 conversion API to use floats to match dpas interfaces and avoid unnecessary float->int conversions Update F -> TF32 conversion API to match naming convention used in cl_intel_bfloat16_conversions (khronos.org)
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12 files changed

+47
-115
lines changed

12 files changed

+47
-115
lines changed

‎IGC/BiFModule/Implementation/IGCBiF_Intrinsics_Dpas.cl

Lines changed: 10 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -417,25 +417,19 @@ half8 __builtin_IB_bf8tohf_8 (char8 a) __attribute__((const));
417417
half16 __builtin_IB_bf8tohf_16(char16 a) __attribute__((const));
418418

419419

420-
// tf32 <--> float float conversion
421-
// tf32 : no igc type for tf32. Use int as *opaque* type for it.
420+
// tf32 <--> float conversion
421+
// tf32 : no igc type for tf32. Use float as *opaque* type for it.
422422
// (tf32: 19 bits, taking 32bit storage)
423423
//
424424
// f -> tf32 conversion builtins (rte rounding mode)
425-
int __builtin_IB_ftotf32_1 (float a) __attribute__((const));
426-
int2 __builtin_IB_ftotf32_2 (float2 a) __attribute__((const));
427-
int3 __builtin_IB_ftotf32_3 (float3 a) __attribute__((const));
428-
int4 __builtin_IB_ftotf32_4 (float4 a) __attribute__((const));
429-
int8 __builtin_IB_ftotf32_8 (float8 a) __attribute__((const));
430-
int16 __builtin_IB_ftotf32_16(float16 a) __attribute__((const));
431-
432-
// tf32 -> f conversion builtins (precise conversion, use shl a, 13)
433-
float __builtin_IB_tf32tof_1 (int a) __attribute__((const));
434-
float2 __builtin_IB_tf32tof_2 (int2 a) __attribute__((const));
435-
float3 __builtin_IB_tf32tof_3 (int3 a) __attribute__((const));
436-
float4 __builtin_IB_tf32tof_4 (int4 a) __attribute__((const));
437-
float8 __builtin_IB_tf32tof_8 (int8 a) __attribute__((const));
438-
float16 __builtin_IB_tf32tof_16(int16 a) __attribute__((const));
425+
float __builtin_IB_ftotf32_1 (float a) __attribute__((const));
426+
float2 __builtin_IB_ftotf32_2 (float2 a) __attribute__((const));
427+
float3 __builtin_IB_ftotf32_3 (float3 a) __attribute__((const));
428+
float4 __builtin_IB_ftotf32_4 (float4 a) __attribute__((const));
429+
float8 __builtin_IB_ftotf32_8 (float8 a) __attribute__((const));
430+
float16 __builtin_IB_ftotf32_16(float16 a) __attribute__((const));
431+
432+
// tf32 -> f conversion is not needed, since every tf32 is already a float
439433

440434
// Stochastic rounding : srnd d a r
441435
// d: bf8 | hf

‎IGC/BiFModule/Implementation/conversions.cl

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -924,32 +924,32 @@ float16 SPIRV_OVERLOADABLE SPIRV_BUILTIN(ConvertBF16ToFINTEL, _v16i16, )(short1
924924

925925
float SPIRV_OVERLOADABLE SPIRV_BUILTIN(RoundFToTF32INTEL, _f32, )(float Value)
926926
{
927-
return as_float(__builtin_IB_ftotf32_1(Value));
927+
return __builtin_IB_ftotf32_1(Value);
928928
}
929929

930930
float2 SPIRV_OVERLOADABLE SPIRV_BUILTIN(RoundFToTF32INTEL, _v2f32, )(float2 Value)
931931
{
932-
return as_float2(__builtin_IB_ftotf32_2(Value));
932+
return __builtin_IB_ftotf32_2(Value);
933933
}
934934

935935
float3 SPIRV_OVERLOADABLE SPIRV_BUILTIN(RoundFToTF32INTEL, _v3f32, )(float3 Value)
936936
{
937-
return as_float3(__builtin_IB_ftotf32_3(Value));
937+
return __builtin_IB_ftotf32_3(Value);
938938
}
939939

940940
float4 SPIRV_OVERLOADABLE SPIRV_BUILTIN(RoundFToTF32INTEL, _v4f32, )(float4 Value)
941941
{
942-
return as_float4(__builtin_IB_ftotf32_4(Value));
942+
return __builtin_IB_ftotf32_4(Value);
943943
}
944944

945945
float8 SPIRV_OVERLOADABLE SPIRV_BUILTIN(RoundFToTF32INTEL, _v8f32, )(float8 Value)
946946
{
947-
return as_float8(__builtin_IB_ftotf32_8(Value));
947+
return __builtin_IB_ftotf32_8(Value);
948948
}
949949

950950
float16 SPIRV_OVERLOADABLE SPIRV_BUILTIN(RoundFToTF32INTEL, _v16f32, )(float16 Value)
951951
{
952-
return as_float16(__builtin_IB_ftotf32_16(Value));
952+
return __builtin_IB_ftotf32_16(Value);
953953
}
954954

955955
/*

‎IGC/BiFModule/Languages/OpenCL/IBiF_dpas.cl

Lines changed: 12 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -62,6 +62,12 @@ INLINE RETTY OVERLOADABLE intel_convert_##FNAME (SRCTY a)
6262
return __builtin_IB_##INTERNAL_FNAME (a); \
6363
}
6464

65+
#define DEFN_INTEL_CVT_NO_OVERLOAD(FNAME, RETTY, SRCTY, INTERNAL_FNAME) \
66+
INLINE RETTY intel_convert_##FNAME (SRCTY a) \
67+
{ \
68+
return __builtin_IB_##INTERNAL_FNAME (a); \
69+
}
70+
6571
//// special conversion/rounding
6672
#define DEFN_INTEL_CVT2(FNAME, RETTY, SRC0TY, SRC1TY, INTERNAL_FNAME) \
6773
INLINE RETTY OVERLOADABLE intel_convert_##FNAME (SRC0TY a, SRC1TY b) \
@@ -488,19 +494,12 @@ DEFN_INTEL_SG16_FDPAS( tf32_tf32_matrix_mad_k8_f32, float2, float2, float, f
488494
DEFN_INTEL_SG16_FDPAS( tf32_tf32_matrix_mad_k8_f32, float4, float4, float2, float8, fdpas_f_f_tf32_tf32_8_4 )
489495
DEFN_INTEL_SG16_FDPAS( tf32_tf32_matrix_mad_k8_f32, float8, float8, float4, float8, fdpas_f_f_tf32_tf32_8_8 )
490496

491-
DEFN_INTEL_CVT( f32_to_tf32, int, float, ftotf32_1 )
492-
DEFN_INTEL_CVT( f32_to_tf32, int2, float2, ftotf32_2 )
493-
DEFN_INTEL_CVT( f32_to_tf32, int3, float3, ftotf32_3 )
494-
DEFN_INTEL_CVT( f32_to_tf32, int4, float4, ftotf32_4 )
495-
DEFN_INTEL_CVT( f32_to_tf32, int8, float8, ftotf32_8 )
496-
DEFN_INTEL_CVT( f32_to_tf32, int16, float16, ftotf32_16 )
497-
498-
DEFN_INTEL_CVT( tf32_to_f32, float, int, tf32tof_1 )
499-
DEFN_INTEL_CVT( tf32_to_f32, float2, int2, tf32tof_2 )
500-
DEFN_INTEL_CVT( tf32_to_f32, float3, int3, tf32tof_3 )
501-
DEFN_INTEL_CVT( tf32_to_f32, float4, int4, tf32tof_4 )
502-
DEFN_INTEL_CVT( tf32_to_f32, float8, int8, tf32tof_8 )
503-
DEFN_INTEL_CVT( tf32_to_f32, float16, int16, tf32tof_16 )
497+
DEFN_INTEL_CVT_NO_OVERLOAD( tfloat32_as_float, float, float, ftotf32_1 )
498+
DEFN_INTEL_CVT_NO_OVERLOAD( tfloat322_as_float2, float2, float2, ftotf32_2 )
499+
DEFN_INTEL_CVT_NO_OVERLOAD( tfloat323_as_float3, float3, float3, ftotf32_3 )
500+
DEFN_INTEL_CVT_NO_OVERLOAD( tfloat324_as_float4, float4, float4, ftotf32_4 )
501+
DEFN_INTEL_CVT_NO_OVERLOAD( tfloat328_as_float8, float8, float8, ftotf32_8 )
502+
DEFN_INTEL_CVT_NO_OVERLOAD( tfloat3216_as_float16, float16, float16, ftotf32_16 )
504503

505504
#endif // cl_intel_subgroup_matrix_multiply_accumulate_tf32
506505

‎IGC/BiFModule/Languages/OpenCL/PreRelease/opencl_cth_pre_release.h

Lines changed: 6 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -2398,19 +2398,12 @@ float4 __attribute__((overloadable)) intel_sub_group_tf32_tf32_matrix_mad_k8_f32
23982398
float8 __attribute__((overloadable)) intel_sub_group_tf32_tf32_matrix_mad_k8_f32(float4 a, float8 b, float8 acc);
23992399

24002400
// Conversions
2401-
int __attribute__((overloadable)) intel_convert_f32_to_tf32(float source);
2402-
int2 __attribute__((overloadable)) intel_convert_f32_to_tf32(float2 source);
2403-
int3 __attribute__((overloadable)) intel_convert_f32_to_tf32(float3 source);
2404-
int4 __attribute__((overloadable)) intel_convert_f32_to_tf32(float4 source);
2405-
int8 __attribute__((overloadable)) intel_convert_f32_to_tf32(float8 source);
2406-
int16 __attribute__((overloadable)) intel_convert_f32_to_tf32(float16 source);
2407-
2408-
float __attribute__((overloadable)) intel_convert_tf32_to_f32(int source);
2409-
float2 __attribute__((overloadable)) intel_convert_tf32_to_f32(int2 source);
2410-
float3 __attribute__((overloadable)) intel_convert_tf32_to_f32(int3 source);
2411-
float4 __attribute__((overloadable)) intel_convert_tf32_to_f32(int4 source);
2412-
float8 __attribute__((overloadable)) intel_convert_tf32_to_f32(int8 source);
2413-
float16 __attribute__((overloadable)) intel_convert_tf32_to_f32(int16 source);
2401+
float intel_convert_tfloat32_as_float( float source);
2402+
float2 intel_convert_tfloat322_as_float2( float2 source);
2403+
float3 intel_convert_tfloat323_as_float3( float3 source);
2404+
float4 intel_convert_tfloat324_as_float4( float4 source);
2405+
float8 intel_convert_tfloat328_as_float8( float8 source);
2406+
float16 intel_convert_tfloat3216_as_float16(float16 source);
24142407

24152408
#endif // cl_intel_subgroup_matrix_multiply_accumulate_tf32
24162409

‎IGC/Compiler/CISACodeGen/EmitVISAPass.cpp

Lines changed: 1 addition & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -8539,7 +8539,6 @@ void EmitPass::EmitGenIntrinsicMessage(llvm::GenIntrinsicInst* inst)
85398539
case GenISAIntrinsic::GenISA_hftobf8:
85408540
case GenISAIntrinsic::GenISA_bf8tohf:
85418541
case GenISAIntrinsic::GenISA_ftotf32:
8542-
case GenISAIntrinsic::GenISA_tf32tof:
85438542
emitfcvt(inst);
85448543
break;
85458544
case GenISAIntrinsic::GenISA_srnd_ftohf:
@@ -21272,8 +21271,7 @@ void EmitPass::emitfcvt(llvm::GenIntrinsicInst* GII)
2127221271
id == GenISAIntrinsic::GenISA_bftof ||
2127321272
id == GenISAIntrinsic::GenISA_hftobf8 ||
2127421273
id == GenISAIntrinsic::GenISA_bf8tohf ||
21275-
id == GenISAIntrinsic::GenISA_ftotf32 ||
21276-
id == GenISAIntrinsic::GenISA_tf32tof)
21274+
id == GenISAIntrinsic::GenISA_ftotf32)
2127721275
{
2127821276
CVariable* tDst = nullptr, *tSrc = nullptr;
2127921277
if (id == GenISAIntrinsic::GenISA_ftobf) {
@@ -21293,10 +21291,6 @@ void EmitPass::emitfcvt(llvm::GenIntrinsicInst* GII)
2129321291
tDst = dst;
2129421292
tSrc = m_currShader->GetNewAlias(src, ISA_TYPE_UB, 0, 0);
2129521293
}
21296-
else if (id == GenISAIntrinsic::GenISA_tf32tof) {
21297-
tDst = dst;
21298-
tSrc = m_currShader->GetNewAlias(src, ISA_TYPE_UD, 0, 0);
21299-
}
2130021294
else if (id == GenISAIntrinsic::GenISA_ftotf32) {
2130121295
tDst = m_currShader->GetNewAlias(dst, ISA_TYPE_UD, 0, 0);
2130221296
// Does not support immediate source of type float, therefore we
@@ -21341,7 +21335,6 @@ void EmitPass::emitfcvt(llvm::GenIntrinsicInst* GII)
2134121335
}
2134221336
if (id == GenISAIntrinsic::GenISA_hftobf8 ||
2134321337
id == GenISAIntrinsic::GenISA_bf8tohf ||
21344-
id == GenISAIntrinsic::GenISA_tf32tof ||
2134521338
id == GenISAIntrinsic::GenISA_ftotf32
2134621339
)
2134721340
{
@@ -21366,7 +21359,6 @@ void EmitPass::emitfcvt(llvm::GenIntrinsicInst* GII)
2136621359
m_encoder->SetSrcSubReg(0, srcOff);
2136721360
if (id == GenISAIntrinsic::GenISA_hftobf8 ||
2136821361
id == GenISAIntrinsic::GenISA_bf8tohf ||
21369-
id == GenISAIntrinsic::GenISA_tf32tof ||
2137021362
id == GenISAIntrinsic::GenISA_ftotf32
2137121363
)
2137221364
{

‎IGC/Compiler/CISACodeGen/WIAnalysis.cpp

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1430,7 +1430,6 @@ WIAnalysis::WIDependancy WIAnalysisRunner::calculate_dep(const CallInst* inst)
14301430
GII_id == GenISAIntrinsic::GenISA_srnd_ftohf ||
14311431
GII_id == GenISAIntrinsic::GenISA_srnd_hftobf8 ||
14321432
GII_id == GenISAIntrinsic::GenISA_ftotf32 ||
1433-
GII_id == GenISAIntrinsic::GenISA_tf32tof ||
14341433
GII_id == GenISAIntrinsic::GenISA_GlobalBufferPointer ||
14351434
GII_id == GenISAIntrinsic::GenISA_LocalBufferPointer ||
14361435
GII_id == GenISAIntrinsic::GenISA_InlinedData ||

‎IGC/Compiler/CISACodeGen/helper.cpp

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -2372,7 +2372,6 @@ namespace IGC
23722372
{
23732373
case GenISAIntrinsic::GenISA_bftof:
23742374
case GenISAIntrinsic::GenISA_bf8tohf:
2375-
case GenISAIntrinsic::GenISA_tf32tof:
23762375
return true;
23772376
default:
23782377
break;

‎IGC/Compiler/Optimizer/OpenCLPasses/DpasFuncs/DpasFuncsResolution.cpp

Lines changed: 2 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -578,17 +578,6 @@ bool DpasFuncsResolution::processCvt(CallInst& CI)
578578
args[1] = ConstantInt::get(intTy, FP_RM); // rounding mode
579579
argslen = 2;
580580
}
581-
else if (funcName.startswith("__builtin_IB_tf32tof_"))
582-
{
583-
// It is a precise conversion, no RM needed!
584-
// Note that sizeof() includes the ending '\0', so need to do -1!
585-
if (!demangleFCvtSuffix(funcName, (int)sizeof("__builtin_IB_tf32tof_") - 1, nullptr, &VecLen, nullptr))
586-
return false;
587-
588-
iid = GenISAIntrinsic::GenISA_tf32tof;
589-
args[0] = CI.getArgOperand(0);
590-
argslen = 1;
591-
}
592581
else
593582
{
594583
return false;
@@ -639,11 +628,9 @@ bool DpasFuncsResolution::processCvt(CallInst& CI)
639628
break;
640629
}
641630
case GenISAIntrinsic::GenISA_ftotf32:
642-
case GenISAIntrinsic::GenISA_tf32tof:
643631
{
644632
if ((n != n0 || n != VecLen) ||
645-
(iid == GenISAIntrinsic::GenISA_ftotf32 && !(EOpnd0Ty->isFloatTy() && ETy->isIntegerTy(32))) ||
646-
(iid == GenISAIntrinsic::GenISA_tf32tof && !(EOpnd0Ty->isIntegerTy(32) && ETy->isFloatTy())))
633+
(iid == GenISAIntrinsic::GenISA_ftotf32 && !(EOpnd0Ty->isFloatTy() && ETy->isFloatTy())))
647634
{
648635
m_ErrorMsg = "Wrong argument types in tf32 conversion functions!";
649636
IGC_ASSERT_MESSAGE(0, "Wrong argument types in tf32 conversion functions!");
@@ -669,8 +656,7 @@ bool DpasFuncsResolution::processCvt(CallInst& CI)
669656
{
670657
cvt = "bf8_cvt";
671658
}
672-
else if (iid == GenISAIntrinsic::GenISA_ftotf32 ||
673-
iid == GenISAIntrinsic::GenISA_tf32tof)
659+
else if (iid == GenISAIntrinsic::GenISA_ftotf32)
674660
{
675661
cvt = "tf32_cvt";
676662
}

‎IGC/GenISAIntrinsics/Intrinsic_definitions.py

Lines changed: 1 addition & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -2927,11 +2927,6 @@
29272927
[("anyint", "bf8 source (as char)")],
29282928
"NoMem"]],
29292929
####################################################################################################
2930-
"GenISA_tf32tof": ["tf32 to float conversion",
2931-
[("anyfloat", "float result"),
2932-
[("anyint", "tf32 source (as int)")],
2933-
"NoMem"]],
2934-
####################################################################################################
29352930
"GenISA_HDCuncompressedwrite": ["XeHP SDV surface compression - HDC flat CCS builtin",
29362931
[("void", "nothing to return"),
29372932
[("anyptr", "ptr location where the value is stored to"),
@@ -2972,16 +2967,11 @@
29722967
"NoMem"]],
29732968
####################################################################################################
29742969
"GenISA_ftotf32": ["float to tf32 conversion",
2975-
[("anyint", "tf32 result (as int)"),
2970+
[("anyfloat", "tf32 result (as float)"),
29762971
[("anyfloat", "float source"),
29772972
("int", "Rounding mode(ERoundingMode)")],
29782973
"NoMem"]],
29792974
####################################################################################################
2980-
"GenISA_tf32tof": ["tf32 to float conversion",
2981-
[("anyfloat", "float result"),
2982-
[("anyint", "tf32 source (as int)")],
2983-
"NoMem"]],
2984-
####################################################################################################
29852975
"GenISA_srnd_hftobf8": ["stochastic rounding: srnd dst src0 src1",
29862976
[("anyint", "dst: bf8 (as ub)"),
29872977
[("anyfloat", "src0: HF"),

‎documentation/visa/instructions/FCVT.md

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -38,7 +38,7 @@ SPDX-License-Identifier: MIT
3838
```
3939
Perform type conversion between FP8 and HF from <src0> to <dst>. FP8 here is BF8, it is an 8-bit float with 1-bit sign, 5-bit exponent, and 2-bit mantissa, aka E5M2. HF-to-BF8 conversion uses the RTE rounding mode (round-to-nearest-even), and denoms are retained. FP8-to-HF is a precise conversion, thus no rounding is involved. BF8 is denoted by type UB as visa has no BF8 type.
4040
41-
{PVC_XT+}It also performs conversion between float and TF32 (tensorfloat, 1-bit sign, 8-bit exponent, and 10-bit mantissa). It also uses RTE for float to TF32. Denorms are flushed to zero. Conversion from TF32 to float is noop as TF32 is a valid F type.
41+
{PVC_XT+}It also performs conversion from float to TF32 (tensorfloat, 1-bit sign, 8-bit exponent, and 10-bit mantissa). It uses RTE for float to TF32. Denorms are flushed to zero. No conversion from TF32 to float, as TF32 is a valid F type.
4242
4343
4444
```
@@ -99,5 +99,5 @@ FCVT (<exec_size>) <dst> <src0>
9999

100100
- If Dst has HF type, Src0 must have UB type (which represents a BF8 value).
101101
- If Dst has UB type (which represents a BF8 value), Src0 must have HF type. NM (NoMask) mask control must be used.
102-
{PVC_XT+}- If Dst has F type, Src0 must have UD (as TF32 value); If Dst has UD type (as TF32 value), Src0 must have F type.
102+
{PVC_XT+}- If Dst has UD type (as TF32 value), Src0 must have F type. Src0 can not be UD type (as TF32 value).
103103

‎visa/HWConformity.cpp

Lines changed: 0 additions & 20 deletions
Original file line numberDiff line numberDiff line change
@@ -8801,26 +8801,6 @@ bool HWConformity::fixFcvt(INST_LIST_ITER i, G4_BB *bb) {
88018801
return true;
88028802
}
88038803

8804-
if (inst->getSrc(0)->getType() == Type_UD) {
8805-
// fcvt a:F b:tf32
8806-
// --> mov a:f b:f (tf32 format is valid f)
8807-
G4_Operand *newSrc;
8808-
if (inst->getSrc(0)->isImm()) {
8809-
float newF = inst->getSrc(0)->asImm()->getFloat();
8810-
newSrc = builder.createImm(newF);
8811-
} else {
8812-
G4_SrcRegRegion *regSrc = inst->getSrc(0)->asSrcRegRegion();
8813-
regSrc->setType(builder, Type_F);
8814-
newSrc = regSrc;
8815-
}
8816-
auto newDst = inst->getDst();
8817-
auto movInst = builder.createMov(inst->getExecSize(), newDst, newSrc,
8818-
inst->getOption(), false);
8819-
bb->insertBefore(i, movInst);
8820-
bb->erase(i);
8821-
return true;
8822-
}
8823-
88248804
if (inst->getDst()->getType() == Type_UD) {
88258805
// fcvt a:tf32 b:f
88268806
// Make sure dst/src0 have the same subreg offset and stride, except for

‎visa/IsaVerification.cpp

Lines changed: 7 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -1053,28 +1053,28 @@ void vISAVerifier::verifyInstructionMove(const CISA_INST *inst) {
10531053

10541054
if (dstType == ISA_TYPE_UB) {
10551055
REPORT_INSTRUCTION(options, src0Type == ISA_TYPE_HF,
1056-
"F_CVT with UB(actually BF8) dst must have HF src");
1056+
"FCVT with UB(actually BF8) dst must have HF src");
10571057
} else if (src0Type == ISA_TYPE_UB) {
10581058
REPORT_INSTRUCTION(options, dstType == ISA_TYPE_HF,
1059-
"F_CVT with UB(actually BF8) src must have HF dst");
1059+
"FCVT with UB(actually BF8) src must have HF dst");
10601060
} else if (dstType == ISA_TYPE_UD) {
10611061
REPORT_INSTRUCTION(options, src0Type == ISA_TYPE_F,
1062-
"F_CVT with UD(actually TF32) dst must have F src");
1062+
"FCVT with UD(actually TF32) dst must have F src");
10631063
} else if (src0Type == ISA_TYPE_UD) {
1064-
REPORT_INSTRUCTION(options, dstType == ISA_TYPE_F,
1065-
"F_CVT with UD(actually TF32) src0 must have F dst");
1064+
REPORT_INSTRUCTION(options, false,
1065+
"FCVT with UD(actually TF32) src0 is not supported");
10661066
}
10671067
else {
10681068
REPORT_INSTRUCTION(options, false,
1069-
"F_CVT must have either UB(actually BF8) dst or src");
1069+
"FCVT must have either UB(actually BF8) dst or src");
10701070
}
10711071

10721072
// Check if NoMask is required
10731073
switch (dstType) {
10741074
case ISA_TYPE_UB:
10751075
{
10761076
REPORT_INSTRUCTION(options, isNoMask(inst->getExecMask()),
1077-
"F_CVT must use noMask for HF to FP8 conversion");
1077+
"FCVT must use noMask for HF to FP8 conversion");
10781078
}
10791079
default:
10801080
break;

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