Fix constant expression handling for 64-bit integer emulation in VC

.

Author: vmustya

IGC/VectorCompiler/lib/GenXCodeGen/GenXUtil.cpp

@@ -1140,15 +1140,23 @@ Region IVSplitter::createSplitRegion(Type *SrcTy, IVSplitter::RegionType RT) {
 // function takes 64-bit constant value (vector or scalar) and splits it
 // into an equivalent vector of 32-bit constant (as if it was Bitcast-ed)
 static void convertI64ToI32(Constant &K, SmallVectorImpl<Constant *> &K32) {
-  auto I64To32 = [](const Constant &K) {
+  auto I64To32 = [](Constant &K) {
     // we expect only scalar types here
     IGC_ASSERT(!isa<VectorType>(K.getType()));
     IGC_ASSERT(K.getType()->isIntegerTy(64));
-    auto *Ty32 = K.getType()->getInt32Ty(K.getContext());
+    auto *Ty32 = Type::getInt32Ty(K.getContext());
     if (isa<UndefValue>(K)) {
       Constant *Undef = UndefValue::get(Ty32);
       return std::make_pair(Undef, Undef);
     }
+    if (isa<ConstantExpr>(K)) {
+      auto *Lo = ConstantExpr::getTrunc(&K, Ty32);
+      auto *Amount = ConstantInt::get(K.getType(), 32);
+      auto *Shift = ConstantExpr::getLShr(&K, Amount);
+      auto *Hi = ConstantExpr::getTrunc(Shift, Ty32);
+      return std::make_pair(Lo, Hi);
+    }
+    IGC_ASSERT_EXIT(isa<ConstantInt>(K));
     auto *KI = cast<ConstantInt>(&K);
     uint64_t Val64 = KI->getZExtValue();
     const auto UI32ValueMask = std::numeric_limits<uint32_t>::max();

IGC/VectorCompiler/test/Emulation/emu_i64_sel_ptr.ll

@@ -1,6 +1,6 @@
 ;=========================== begin_copyright_notice ============================
 ;
-; Copyright (C) 2022 Intel Corporation
+; Copyright (C) 2022-2023 Intel Corporation
 ;
 ; SPDX-License-Identifier: MIT
 ;
@@ -70,3 +70,17 @@ define <8 x i8*> @test_vector(<8 x i1> %cond, <8 x i8*> %left, <8 x i8*> %right)
   %res = select <8 x i1> %cond, <8 x i8*> %left, <8 x i8*> %right
   ret <8 x i8*> %res
 }
+
+; CHECK-LABEL: @test_constexpr
+define float addrspace(1)* @test_constexpr(i1 %cond) {
+  ; CHECK: [[SEL_LO:%[^ ]+]] = select i1 %cond, <1 x i32> zeroinitializer, <1 x i32> <i32 ptrtoint (float addrspace(1)* addrspacecast (float addrspace(4)* null to float addrspace(1)*) to i32)>
+  ; CHECK: [[SEL_HI:%[^ ]+]] = select i1 %cond, <1 x i32> zeroinitializer, <1 x i32> <i32 trunc (i64 lshr (i64 ptrtoint (float addrspace(1)* addrspacecast (float addrspace(4)* null to float addrspace(1)*) to i64), i64 32) to i32)>
+  ; CHECK: [[PART_JOIN:%[^ ]+]] = call <2 x i32> @llvm.genx.wrregioni.v2i32.v1i32.i16.i1(<2 x i32> undef, <1 x i32> [[SEL_LO]], i32 0, i32 1, i32 2, i16 0, i32 undef, i1 true)
+  ; CHECK: [[JOIN:%[^ ]+]] = call <2 x i32> @llvm.genx.wrregioni.v2i32.v1i32.i16.i1(<2 x i32> [[PART_JOIN]], <1 x i32> [[SEL_HI]], i32 0, i32 1, i32 2, i16 4, i32 undef, i1 true)
+  ; CHECK: [[VCAST:%[^ ]+]] = bitcast <2 x i32> [[JOIN]] to <1 x i64>
+  ; CHECK: [[ICAST:%[^ ]+]] = bitcast <1 x i64> [[VCAST]] to i64
+  ; CHECK: [[ITP:%[^ ]+]] = inttoptr i64 [[ICAST]] to float addrspace(1)*
+  ; CHECK: ret float addrspace(1)* [[ITP]]
+  %res = select i1 %cond, float addrspace(1)* null, float addrspace(1)* addrspacecast(float addrspace(4)* null to float addrspace(1)*)
+  ret float addrspace(1)* %res
+}