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houjenkosys_zuul
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sys_zuul
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Make ForcePSBestSIMD RegKey only applicable to the first stage while staged compilation is on
Platforms: All Change-Id: I553319a46f37e87bab9f6b22ecd86a8df272deba Related-to: SCSP-19136 Resolves:
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4 files changed

+4
-4
lines changed

4 files changed

+4
-4
lines changed

IGC/Compiler/CISACodeGen/EmitVISAPass.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -399,7 +399,7 @@ bool EmitPass::runOnFunction(llvm::Function& F)
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400400
m_FGA = getAnalysisIfAvailable<GenXFunctionGroupAnalysis>();
401401

402-
if ((IGC_IS_FLAG_ENABLED(ForcePSBestSIMD) || IsStage1BestPerf(m_pCtx->m_CgFlag, m_pCtx->m_StagingCtx)) && m_SimdMode == SIMDMode::SIMD8)
402+
if ((IsStage1BestPerf(m_pCtx->m_CgFlag, m_pCtx->m_StagingCtx)) && m_SimdMode == SIMDMode::SIMD8)
403403
{
404404
/* Don't do SIMD8 if SIMD16 has no spill */
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auto Iter = m_shaders.find(&F);

IGC/Compiler/CISACodeGen/PixelShaderCodeGen.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1123,7 +1123,7 @@ namespace IGC
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}
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if (simdMode == SIMDMode::SIMD16 && EP.m_ShaderMode == ShaderDispatchMode::NOT_APPLICABLE)
11251125
{
1126-
if (IGC_IS_FLAG_ENABLED(ForcePSBestSIMD) || IsStage1BestPerf(ctx->m_CgFlag, ctx->m_StagingCtx))
1126+
if (IsStage1BestPerf(ctx->m_CgFlag, ctx->m_StagingCtx))
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{
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return true;
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}

IGC/Compiler/CISACodeGen/ShaderCodeGen.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -760,7 +760,7 @@ namespace IGC
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bool earlyExit =
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ctx->getCompilerOption().pixelShaderDoNotAbortOnSpill ? false : true;
762762

763-
if (IGC_IS_FLAG_ENABLED(ForcePSBestSIMD) || IsStage1BestPerf(ctx->m_CgFlag, ctx->m_StagingCtx))
763+
if (IsStage1BestPerf(ctx->m_CgFlag, ctx->m_StagingCtx))
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{
765765
// don't retry SIMD16 for ForcePSBestSIMD
766766
if( SimdEarlyCheck( ctx ) && ( !ctx->m_retryManager.IsLastTry( ctx ) ) )

IGC/common/igc_flags.def

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -334,7 +334,7 @@ DECLARE_IGC_REGKEY(bool, PixelShaderDoNotAbortOnSpill, false, "Do not abort on
334334
DECLARE_IGC_REGKEY(DWORD, ForcePixelShaderSIMDMode, 0, "Setting it to values def in igc.h will force SIMD mode compilation for pixel shaders. Note that only SIMD8 is compiled unless other ForcePixelShaderSIMD* are also selected", false)
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DECLARE_IGC_REGKEY(DWORD, StagedCompilationExperiments, 0, "Experiment with staged compilation when != 0", false)
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DECLARE_IGC_REGKEY(bool, StagedCompilation, false, "Enable staged compilation", false)
337-
DECLARE_IGC_REGKEY(bool, ForcePSBestSIMD, false, "Force Pixel shader to return the best SIMD, either SIMD16 or SIMD8", false)
337+
DECLARE_IGC_REGKEY(bool, ForcePSBestSIMD, false, "Force Pixel shader to return the best SIMD, either SIMD16 or SIMD8. When StagedCompilation is on, this only affects to the first stage", false)
338338
DECLARE_IGC_REGKEY(bool, SkipTREarlyExitCheck, false, "Skip SIMD16 early exit check in ShaderCodeGen", false)
339339
DECLARE_IGC_REGKEY(bool, EnableTCSHWBarriers, false, "Enable TCS pass with HW barriers support. Default TCS pass is TCS pass with multiple continuation functions.", false)
340340
DECLARE_IGC_REGKEY(bool, ForceMCFBarriers, false, "Force TCS pass with MCF (SW) barriers support. Default TCS pass is TCS pass with multiple continuation functions.", false)

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