Skip to content

Commit affc57b

Browse files
lukaszgotszaldinteligcbot
lukaszgotszaldintel
authored and
igcbot
committed
refactor assertion statements
refactor assertion statements
1 parent fccd4d8 commit affc57b

File tree

7 files changed

+44
-38
lines changed

7 files changed

+44
-38
lines changed

‎IGC/VectorCompiler/lib/GenXCodeGen/GenXBaling.cpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -977,8 +977,8 @@ void GenXBaling::processFuncPointer(Instruction *Inst) {
977977

978978
void GenXBaling::processRdWrPredefReg(Instruction *Inst) {
979979
auto *CI = dyn_cast<CallInst>(Inst);
980-
IGC_ASSERT((CI && GenXIntrinsic::isReadWritePredefReg(Inst)) &&
981-
"genx.read/write.reg expected");
980+
IGC_ASSERT_MESSAGE((CI && GenXIntrinsic::isReadWritePredefReg(Inst)),
981+
"genx.read/write.reg expected");
982982
BaleInfo BI(BaleInfo::REGINTR);
983983
setBaleInfo(Inst, BI);
984984
}

‎IGC/VectorCompiler/lib/GenXCodeGen/GenXCisaBuilder.cpp

Lines changed: 2 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -3562,9 +3562,8 @@ void GenXKernelBuilder::buildIntrinsic(CallInst *CI, unsigned IntrinID,
35623562
case llvm::GenXIntrinsic::genx_svm_atomic_xor:
35633563
break;
35643564
default:
3565-
IGC_ASSERT(false &&
3566-
"Trying to get bit width for non-svm atomic inst");
3567-
break;
3565+
IGC_ASSERT_MESSAGE(0, "Trying to get bit width for non-svm atomic inst");
3566+
break;
35683567
}
35693568
#endif // !NDEBUG
35703569
auto* T = AI.isRet() ? CI->getType() : CI->getArgOperand(AI.getArgIdx())->getType();

‎IGC/VectorCompiler/lib/GenXCodeGen/GenXCoalescing.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1579,7 +1579,7 @@ void GenXCoalescing::coalesceOutputArgs(FunctionGroup *FG) {
15791579
continue;
15801580

15811581
for (auto Arg : OutputArgs) {
1582-
IGC_ASSERT(CI && "No genx.output.1 intrinsic for output argument");
1582+
IGC_ASSERT_MESSAGE(CI, "No genx.output.1 intrinsic for output argument");
15831583

15841584
// This is the final value stored into the output argument.
15851585
// If this is coalesced into kernel argument, nothing to do.

‎IGC/VectorCompiler/lib/GenXCodeGen/GenXLowering.cpp

Lines changed: 17 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -1175,7 +1175,8 @@ bool GenXLowering::translateSLMOWord(CallInst* CI, unsigned IID) {
11751175
// 4-oword is 64 bytes, using simd16 dword gather-scaled
11761176
// 8-oword is 128 bytes, using 2*simd16 dword gather-scaled
11771177
unsigned DWordCnt = (EltSize * EltCount) / 32;
1178-
assert(DWordCnt == 4 || DWordCnt == 8 || DWordCnt == 16 || DWordCnt == 32);
1178+
IGC_ASSERT(DWordCnt == 4 || DWordCnt == 8 || DWordCnt == 16 ||
1179+
DWordCnt == 32);
11791180
unsigned SimdWidth = (DWordCnt == 32) ? 16 : DWordCnt;
11801181
auto NewVT = IGCLLVM::FixedVectorType::get(CIntTy, DWordCnt);
11811182
auto GatherVT = IGCLLVM::FixedVectorType::get(CIntTy, SimdWidth);
@@ -1270,7 +1271,8 @@ bool GenXLowering::translateSLMOWord(CallInst* CI, unsigned IID) {
12701271
// 4-oword is 64 bytes, using simd16 dword scatter-scaled
12711272
// 8-oword is 128 bytes, using 2*simd16 dword scatter-scaled
12721273
unsigned DWordCnt = (EltSize * EltCount) / 32;
1273-
assert(DWordCnt == 4 || DWordCnt == 8 || DWordCnt == 16 || DWordCnt == 32);
1274+
IGC_ASSERT(DWordCnt == 4 || DWordCnt == 8 || DWordCnt == 16 ||
1275+
DWordCnt == 32);
12741276
auto NewVT = IGCLLVM::FixedVectorType::get(CIntTy, DWordCnt);
12751277
IGC_ASSERT_MESSAGE(CastInst::isBitCastable(NewVT, OrigVT),
12761278
"We expect resulting vectors to be bitcastable");
@@ -3997,7 +3999,7 @@ bool GenXLowering::lowerBoolScalarSelect(SelectInst *SI) {
39973999
Phi->takeName(SI);
39984000
Phi->addIncoming(SI->getTrueValue(), BB1);
39994001
Phi->addIncoming(SI->getFalseValue(), BB2);
4000-
Phi->setDebugLoc(SI->getDebugLoc());
4002+
Phi->setDebugLoc(SI->getDebugLoc());
40014003
SI->replaceAllUsesWith(Phi);
40024004
ToErase.push_back(SI);
40034005
// Split the (critical) edge from BB1 to BB4 to avoid having critical edge.
@@ -5307,9 +5309,9 @@ bool GenXLowering::lowerLzd(Instruction *Inst) {
53075309
#define SYCL_SLM_AS 3
53085310
bool GenXLowering::lowerLLVMMaskedLoad(CallInst* CallOp) {
53095311
auto PtrV = CallOp->getArgOperand(0);
5310-
assert(PtrV->getType()->isPointerTy());
5312+
IGC_ASSERT(PtrV->getType()->isPointerTy());
53115313
auto AS = cast<PointerType>(PtrV->getType())->getAddressSpace();
5312-
assert(AS != SYCL_SLM_AS && "do not expect masked load from SLM");
5314+
IGC_ASSERT_MESSAGE(AS != SYCL_SLM_AS, "do not expect masked load from SLM");
53135315
auto DTy = CallOp->getType();
53145316
// convert to unaligned-block-load then select
53155317
std::string IntrName =
@@ -5331,9 +5333,9 @@ bool GenXLowering::lowerLLVMMaskedLoad(CallInst* CallOp) {
53315333

53325334
bool GenXLowering::lowerLLVMMaskedStore(CallInst* CallOp) {
53335335
auto PtrV = CallOp->getArgOperand(1);
5334-
assert(PtrV->getType()->isPointerTy());
5336+
IGC_ASSERT(PtrV->getType()->isPointerTy());
53355337
auto AS = cast<PointerType>(PtrV->getType())->getAddressSpace();
5336-
assert(AS != SYCL_SLM_AS && "do not expected masked store to SLM");
5338+
IGC_ASSERT_MESSAGE(AS != SYCL_SLM_AS, "do not expected masked store to SLM");
53375339
auto DTV = CallOp->getArgOperand(0);
53385340
auto DL = CallOp->getDebugLoc();
53395341
// convert to unaligned-block-load then select
@@ -5369,11 +5371,12 @@ bool GenXLowering::lowerLLVMMaskedGather(CallInst* CallOp) {
53695371
auto MaskV = CallOp->getArgOperand(2);
53705372
auto OldV = CallOp->getArgOperand(3);
53715373
auto DTy = CallOp->getType();
5372-
assert(PtrV->getType()->isVectorTy() && DTy->isVectorTy());
5374+
IGC_ASSERT(PtrV->getType()->isVectorTy());
5375+
IGC_ASSERT(DTy->isVectorTy());
53735376
auto PtrETy = cast<VectorType>(PtrV->getType())->getElementType();
5374-
assert(PtrETy->isPointerTy());
5377+
IGC_ASSERT(PtrETy->isPointerTy());
53755378
auto AS = cast<PointerType>(PtrETy)->getAddressSpace();
5376-
assert(AS != SYCL_SLM_AS && "do not expect masked gather from SLM");
5379+
IGC_ASSERT_MESSAGE(AS != SYCL_SLM_AS, "do not expect masked gather from SLM");
53775380
auto EltTy = cast<VectorType>(DTy)->getElementType();
53785381
auto NumElts = cast<IGCLLVM::FixedVectorType>(DTy)->getNumElements();
53795382
auto EltBytes = EltTy->getPrimitiveSizeInBits() / 8;
@@ -5427,11 +5430,12 @@ bool GenXLowering::lowerLLVMMaskedScatter(CallInst* CallOp) {
54275430
auto PtrV = CallOp->getArgOperand(1);
54285431
auto MaskV = CallOp->getArgOperand(3);
54295432
auto DTy = DataV->getType();
5430-
assert(PtrV->getType()->isVectorTy() && DTy->isVectorTy());
5433+
IGC_ASSERT(PtrV->getType()->isVectorTy());
5434+
IGC_ASSERT(DTy->isVectorTy());
54315435
auto PtrETy = cast<VectorType>(PtrV->getType())->getElementType();
5432-
assert(PtrETy->isPointerTy());
5436+
IGC_ASSERT(PtrETy->isPointerTy());
54335437
auto AS = cast<PointerType>(PtrETy)->getAddressSpace();
5434-
assert(AS != SYCL_SLM_AS && "do not expect masked scatter to SLM");
5438+
IGC_ASSERT_MESSAGE(AS != SYCL_SLM_AS, "do not expect masked scatter to SLM");
54355439
auto EltTy = cast<VectorType>(DTy)->getElementType();
54365440
auto NumElts = cast<IGCLLVM::FixedVectorType>(DTy)->getNumElements();
54375441
auto EltBytes = EltTy->getPrimitiveSizeInBits() / 8;

‎IGC/VectorCompiler/lib/GenXCodeGen/GenXPatternMatch.cpp

Lines changed: 19 additions & 17 deletions
Original file line numberDiff line numberDiff line change
@@ -2877,9 +2877,9 @@ bool GenXPatternMatch::simplifyVolatileGlobals(Function *F) {
28772877
// of log2 of original vector;
28782878
// input vector consists of only positive integer or only one positive integer
28792879
static Constant *getFloorLog2(const Constant *C) {
2880-
IGC_ASSERT(C && "getFloorLog2 get nullptr");
2881-
IGC_ASSERT(C->getType()->isIntOrIntVectorTy() &&
2882-
"Error: getFloorLog2 get not int or vector of int type");
2880+
IGC_ASSERT_MESSAGE(C, "getFloorLog2 get nullptr");
2881+
IGC_ASSERT_MESSAGE(C->getType()->isIntOrIntVectorTy(),
2882+
"Error: getFloorLog2 get not int or vector of int type");
28832883
if (C->getType()->isVectorTy()) {
28842884
VectorType *Ty = cast<VectorType>(C->getType());
28852885
SmallVector<Constant *, 4> Elts;
@@ -2903,7 +2903,7 @@ static Constant *getFloorLog2(const Constant *C) {
29032903
// return true if Value is constant data power 2 value
29042904
// input operand - value
29052905
bool isSuitableSdivSremPow2Operand(const Value *Operand) {
2906-
IGC_ASSERT(Operand && "nullptr in isSuitableSdivSremPow2Operand");
2906+
IGC_ASSERT_MESSAGE(Operand, "nullptr in isSuitableSdivSremPow2Operand");
29072907
if (!isa<Constant>(Operand)) // constant data vector or constant
29082908
return false;
29092909
if (PatternMatch::match(Operand, PatternMatch::m_Negative()))
@@ -2912,8 +2912,9 @@ bool isSuitableSdivSremPow2Operand(const Value *Operand) {
29122912
if (!Operand->getType()->isIntOrIntVectorTy(genx::DWordBits))
29132913
return false; // not int and not vector of int, or width wrong
29142914
Type *InstElementTy = Operand->getType()->getScalarType();
2915-
IGC_ASSERT(InstElementTy &&
2916-
"ERROR: logic error in is isSuitableSdivSremPow2DecomposeInst");
2915+
IGC_ASSERT_MESSAGE(
2916+
InstElementTy,
2917+
"ERROR: logic error in is isSuitableSdivSremPow2DecomposeInst");
29172918
return PatternMatch::match(Operand, PatternMatch::m_Power2());
29182919
}
29192920

@@ -2925,18 +2926,19 @@ bool isSuitableSdivSremPow2Operand(const Value *Operand) {
29252926
// intWidth = 32
29262927
// x / y = ashr( x + lshr( ashr(x, intWidth - 1), intWidth - log2(y)), log2(y))
29272928
static void decomposeSdivPow2(BinaryOperator &Sdiv) {
2928-
IGC_ASSERT(Sdiv.getOpcode() == Instruction::SDiv &&
2929-
"Error: try to decompose sdiv for not sdiv instruction");
2930-
IGC_ASSERT(isSuitableSdivSremPow2Operand(Sdiv.getOperand(1)) &&
2931-
"Error: try to decompose sdiv for not suitable instruction");
2929+
IGC_ASSERT_MESSAGE(Sdiv.getOpcode() == Instruction::SDiv,
2930+
"Error: try to decompose sdiv for not sdiv instruction");
2931+
IGC_ASSERT_MESSAGE(
2932+
isSuitableSdivSremPow2Operand(Sdiv.getOperand(1)),
2933+
"Error: try to decompose sdiv for not suitable instruction");
29322934

29332935
const Twine Name = "genxSdivOpt";
29342936
Value *Op0 = Sdiv.getOperand(0);
29352937
Constant *Op1 = cast<Constant>(Sdiv.getOperand(1));
29362938

29372939
Type *SdivTy = Sdiv.getType();
29382940
Type *ElementTy = SdivTy->getScalarType();
2939-
IGC_ASSERT(ElementTy && "ERROR: logic error in decomposeSdivPow2");
2941+
IGC_ASSERT_MESSAGE(ElementTy, "ERROR: logic error in decomposeSdivPow2");
29402942
unsigned ElementBitWidth = ElementTy->getIntegerBitWidth();
29412943
unsigned OperandWidth =
29422944
SdivTy->isVectorTy()
@@ -2957,7 +2959,7 @@ static void decomposeSdivPow2(BinaryOperator &Sdiv) {
29572959
createConstant(OperandWidth, ElementTy, ElementBitWidth);
29582960

29592961
Constant *Log2Op1 = getFloorLog2(Op1);
2960-
IGC_ASSERT(Log2Op1 != nullptr && "getLog2 return nullptr");
2962+
IGC_ASSERT_MESSAGE(Log2Op1 != nullptr, "getLog2 return nullptr");
29612963

29622964
Value *ShiftSize = Builder.CreateSub(VecBitWidth, Log2Op1, Name);
29632965
// if op0 is negative, Signdetect all ones, else all zeros
@@ -2979,16 +2981,16 @@ void GenXPatternMatch::visitSDiv(BinaryOperator &I) {
29792981
// suppose that later sdiv operation will be optimized by decomposeSdivPow2
29802982
// x % y = x - y * (x / y)
29812983
static void decomposeSremPow2(BinaryOperator &Srem) {
2982-
IGC_ASSERT(Srem.getOpcode() == Instruction::SRem &&
2983-
"Error: try to decomposeSrem not srem");
2984-
IGC_ASSERT(isSuitableSdivSremPow2Operand(Srem.getOperand(1)) &&
2985-
"Error: try to decomposeSrem for not suitable Operand 1");
2984+
IGC_ASSERT_MESSAGE(Srem.getOpcode() == Instruction::SRem,
2985+
"Error: try to decomposeSrem not srem");
2986+
IGC_ASSERT_MESSAGE(isSuitableSdivSremPow2Operand(Srem.getOperand(1)),
2987+
"Error: try to decomposeSrem for not suitable Operand 1");
29862988
const Twine Name = "genxSremOpt";
29872989
Value *Op0 = Srem.getOperand(0);
29882990
Constant *Op1 = cast<Constant>(Srem.getOperand(1));
29892991

29902992
Type *SremTy = Srem.getType();
2991-
IGC_ASSERT(SremTy && "ERROR: logic error in decomposeSremPow2");
2993+
IGC_ASSERT_MESSAGE(SremTy, "ERROR: logic error in decomposeSremPow2");
29922994

29932995
IRBuilder<> Builder(&Srem);
29942996

‎IGC/VectorCompiler/lib/GenXCodeGen/GenXSimdCFConformance.cpp

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -4146,7 +4146,8 @@ void GenXSimdCFConformance::replaceGetEMUse(Instruction *Inst,
41464146
} else {
41474147
// Replace with lowered EM
41484148
auto it = LoweredEMValsMap.find(JPData.getRealEM());
4149-
IGC_ASSERT(it != LoweredEMValsMap.end() && "Should be checked earlier");
4149+
IGC_ASSERT_MESSAGE(it != LoweredEMValsMap.end(),
4150+
"Should be checked earlier");
41504151
Instruction *LoweredEM = cast<Instruction>(it->second);
41514152
Inst->setOperand(i, LoweredEM);
41524153

‎IGC/VectorCompiler/lib/GenXCodeGen/GenXVectorCombiner.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -134,7 +134,7 @@ bool GenXVectorCombiner::isSupportedGenXIntrinsic(GenXIntrinsic::ID IdCode) {
134134
case GenXIntrinsic::genx_absi:
135135
return true;
136136
}
137-
IGC_ASSERT(false);
137+
IGC_ASSERT(0);
138138
return false;
139139
}
140140

0 commit comments

Comments
 (0)