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aratajewpszymich
aratajew
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pszymich
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Support for RT_GLOBAL_BUFFER_POINTER implicit arg in GlobalStateBuffer
There are several cases when calling `intel_get_implicit_dispatch_globals` builtin from function `F` causes a crash: 1. Function F definition is compiled in ModuleA, but called through stackcall in ModuleB. 2. Function F has "referenced-indirectly" attribute. 3. Function F is a recurrent function. In these three cases, `RT_GLOBAL_BUFFER_POINTER` implicit argument must be passed through GlobalStateBuffer, since 'F' is called through a stackcall.
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15 files changed

+99
-66
lines changed

15 files changed

+99
-66
lines changed

‎IGC/AdaptorCommon/ImplicitArgs.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -90,7 +90,7 @@ static const std::vector<ImplicitArg> IMPLICIT_ARGS = {
9090
ImplicitArg(ImplicitArg::SYNC_BUFFER, "syncBuffer", ImplicitArg::GLOBALPTR, WIAnalysis::UNIFORM_GLOBAL, 1, ImplicitArg::ALIGN_PTR, false, GenISAIntrinsic::GenISA_getSyncBuffer),
9191

9292
// raytracing
93-
ImplicitArg(ImplicitArg::RT_GLOBAL_BUFFER_POINTER, "globalPointer", ImplicitArg::GLOBALPTR, WIAnalysis::UNIFORM_GLOBAL, 1, ImplicitArg::ALIGN_GRF, false),
93+
ImplicitArg(ImplicitArg::RT_GLOBAL_BUFFER_POINTER, "globalPointer", ImplicitArg::GLOBALPTR, WIAnalysis::UNIFORM_GLOBAL, 1, ImplicitArg::ALIGN_GRF, false, GenISAIntrinsic::GenISA_getRtGlobalBufferPtr),
9494
ImplicitArg(ImplicitArg::RT_LOCAL_BUFFER_POINTER, "localPointer", ImplicitArg::GLOBALPTR, WIAnalysis::UNIFORM_GLOBAL, 1, ImplicitArg::ALIGN_QWORD, false),
9595
ImplicitArg(ImplicitArg::RT_INLINED_DATA, "inlinedData", ImplicitArg::GLOBALPTR, WIAnalysis::UNIFORM_GLOBAL, 2, ImplicitArg::ALIGN_GRF, false),
9696
ImplicitArg(ImplicitArg::RT_STACK_ID, "stackID", ImplicitArg::SHORT, WIAnalysis::RANDOM, 16, ImplicitArg::ALIGN_GRF, false),

‎IGC/AdaptorCommon/RayTracing/RayTracingIntrinsicResolution.cpp

Lines changed: 7 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -49,11 +49,12 @@ class RayTracingIntrinsicResolution : public FunctionPass, public InstVisitor<Ra
4949

5050
static char ID;
5151
private:
52-
Argument* getImplicitArg(Function *F, ImplicitArg::ArgType argType);
52+
Value* getImplicitArg(Function *F, ImplicitArg::ArgType argType);
5353
private:
5454
ImplicitArgs m_implicitArgs;
5555
bool Changed;
5656
CodeGenContext* m_CGCtx = nullptr;
57+
IGCMD::MetaDataUtils* m_pMdUtils = nullptr;
5758
};
5859

5960
#define PASS_FLAG "raytracing-intrinsic-resolution"
@@ -64,10 +65,10 @@ IGC_INITIALIZE_PASS_BEGIN(RayTracingIntrinsicResolution, PASS_FLAG, PASS_DESCRIP
6465
IGC_INITIALIZE_PASS_DEPENDENCY(MetaDataUtilsWrapper)
6566
IGC_INITIALIZE_PASS_END(RayTracingIntrinsicResolution, PASS_FLAG, PASS_DESCRIPTION, PASS_CFG_ONLY, PASS_ANALYSIS)
6667

67-
Argument* RayTracingIntrinsicResolution::getImplicitArg(
68+
Value* RayTracingIntrinsicResolution::getImplicitArg(
6869
Function *F, ImplicitArg::ArgType argType)
6970
{
70-
return m_implicitArgs.getImplicitArg(*F, argType);
71+
return m_implicitArgs.getImplicitArgValue(*F, argType, m_pMdUtils);
7172
}
7273

7374
RayTracingIntrinsicResolution::RayTracingIntrinsicResolution() : FunctionPass(ID) {
@@ -121,16 +122,16 @@ void RayTracingIntrinsicResolution::visitCallInst(CallInst &CI)
121122

122123
bool RayTracingIntrinsicResolution::runOnFunction(Function &F)
123124
{
124-
auto *pMdUtils = getAnalysis<MetaDataUtilsWrapper>().getMetaDataUtils();
125+
m_pMdUtils = getAnalysis<MetaDataUtilsWrapper>().getMetaDataUtils();
125126
m_CGCtx = getAnalysis<CodeGenContextWrapper>().getCodeGenContext();
126127

127-
if (pMdUtils->findFunctionsInfoItem(&F) == pMdUtils->end_FunctionsInfo())
128+
if (m_pMdUtils->findFunctionsInfoItem(&F) == m_pMdUtils->end_FunctionsInfo())
128129
return false;
129130

130131
Changed = false;
131132
m_implicitArgs = ImplicitArgs(
132133
F,
133-
pMdUtils);
134+
m_pMdUtils);
134135
visit(F);
135136

136137
return Changed;

‎IGC/AdaptorOCL/OCL/sp/zebin_builder.cpp

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -564,6 +564,7 @@ void ZEBinaryBuilder::addKernelExecEnv(const SOpenCLKernelInfo& annotations,
564564
}
565565
env.eu_thread_count = annotations.m_executionEnvironment.numThreads;
566566
env.has_sample = annotations.m_executionEnvironment.HasSample;
567+
env.has_rtcalls = annotations.m_executionEnvironment.HasRTCalls;
567568
}
568569

569570
void ZEBinaryBuilder::addFunctionExecEnv(const SOpenCLKernelInfo& annotations,
@@ -576,6 +577,7 @@ void ZEBinaryBuilder::addFunctionExecEnv(const SOpenCLKernelInfo& annotations,
576577
env.grf_count = annotations.m_executionEnvironment.NumGRFRequired;
577578
env.simd_size = annotations.m_executionEnvironment.CompiledSIMDSize;
578579
env.barrier_count = zeFuncAttr.f_BarrierCount;
580+
env.has_rtcalls = zeFuncAttr.f_hasRTCalls;
579581
}
580582

581583
void ZEBinaryBuilder::addLocalIds(uint32_t simdSize, uint32_t grfSize,

‎IGC/Compiler/CISACodeGen/CISABuilder.cpp

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -5686,6 +5686,7 @@ namespace IGC
56865686
}
56875687

56885688
void CEncoder::CreateFuncAttributeTable(VISAKernel* pMainKernel) {
5689+
ModuleMetaData* modMD = m_program->GetContext()->getModuleMetaData();
56895690
SProgramOutput *pOutput = m_program->ProgramOutput();
56905691
void *&buffer = pOutput->m_funcAttributeTable;
56915692
unsigned &bufferSize = pOutput->m_funcAttributeTableSize;
@@ -5727,8 +5728,9 @@ namespace IGC
57275728
uint8_t isExternal = F->hasFnAttribute("referenced-indirectly") ? 1 : 0;
57285729
// Set per-function barrier count from vISA information.
57295730
uint32_t barrierCnt = jitInfo->numBarriers;
5731+
uint8_t hasRTCalls = (uint8_t)modMD->FuncMD[F].hasSyncRTCalls;
57305732
attrs.emplace_back(entry.f_isKernel, isExternal, barrierCnt, entry.f_privateMemPerThread,
5731-
entry.f_spillMemPerThread, F->getName().str());
5733+
entry.f_spillMemPerThread, F->getName().str(), hasRTCalls);
57325734
attribTable.push_back(entry);
57335735
}
57345736

‎IGC/Compiler/CISACodeGen/EmitVISAPass.cpp

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -8030,6 +8030,7 @@ void EmitPass::EmitGenIntrinsicMessage(llvm::GenIntrinsicInst* inst)
80308030
case GenISAIntrinsic::GenISA_getStageInGridOrigin:
80318031
case GenISAIntrinsic::GenISA_getStageInGridSize:
80328032
case GenISAIntrinsic::GenISA_getSyncBuffer:
8033+
case GenISAIntrinsic::GenISA_getRtGlobalBufferPtr:
80338034
emitImplicitArgIntrinsic(inst);
80348035
break;
80358036
case GenISAIntrinsic::GenISA_AsyncStackID:

‎IGC/Compiler/CISACodeGen/WIAnalysis.cpp

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1352,6 +1352,7 @@ WIAnalysis::WIDependancy WIAnalysisRunner::calculate_dep(const CallInst* inst)
13521352
GII_id == GenISAIntrinsic::GenISA_getStageInGridOrigin ||
13531353
GII_id == GenISAIntrinsic::GenISA_getStageInGridSize ||
13541354
GII_id == GenISAIntrinsic::GenISA_getSyncBuffer ||
1355+
GII_id == GenISAIntrinsic::GenISA_getRtGlobalBufferPtr ||
13551356
GII_id == GenISAIntrinsic::GenISA_GetImplicitBufferPtr ||
13561357
GII_id == GenISAIntrinsic::GenISA_GetLocalIdBufferPtr ||
13571358
GII_id == GenISAIntrinsic::GenISA_staticConstantPatchValue)
@@ -1393,6 +1394,7 @@ WIAnalysis::WIDependancy WIAnalysisRunner::calculate_dep(const CallInst* inst)
13931394
case GenISAIntrinsic::GenISA_getStageInGridOrigin:
13941395
case GenISAIntrinsic::GenISA_getStageInGridSize:
13951396
case GenISAIntrinsic::GenISA_getSyncBuffer:
1397+
case GenISAIntrinsic::GenISA_getRtGlobalBufferPtr:
13961398
return ImplicitArgs::getArgDep(GII_id);
13971399
}
13981400

‎IGC/Compiler/Optimizer/OpenCLPasses/WIFuncs/WIFuncResolution.cpp

Lines changed: 38 additions & 50 deletions
Original file line numberDiff line numberDiff line change
@@ -18,6 +18,8 @@ SPDX-License-Identifier: MIT
1818
#include <llvmWrapper/Support/Alignment.h>
1919
#include <llvmWrapper/IR/DerivedTypes.h>
2020

21+
#include <cstddef>
22+
2123
using namespace llvm;
2224
using namespace IGC;
2325

@@ -213,6 +215,22 @@ void WIFuncResolution::visitCallInst(CallInst& CI)
213215
214216
*************************************************************************************************/
215217

218+
#pragma pack(push, 1)
219+
namespace packed
220+
{
221+
#include "implicit_args_struct.h"
222+
}
223+
#pragma pack(pop)
224+
225+
#undef IMPLICIT_ARGS_STRUCT_H_
226+
#include "implicit_args_struct.h"
227+
228+
// According to the ABI specification, implicit_args struct must be naturally aligned.
229+
// To ensure that offsets to struct members are compiler-independent, it is necessary to
230+
// align struct member offset to be divisible by the size of the member. It implicates
231+
// inserting an additional padding member in some cases.
232+
static_assert(sizeof(packed::implicit_args) == sizeof(implicit_args), "Implicit args struct is not properly aligned!");
233+
216234
// Structure of side buffer generated by NEO:
217235
//struct implicit_args {
218236
// uint8_t struct_size;
@@ -233,6 +251,8 @@ void WIFuncResolution::visitCallInst(CallInst& CI)
233251
// uint32_t group_count_x;
234252
// uint32_t group_count_y;
235253
// uint32_t group_count_z;
254+
// uint32_t padding0;
255+
// uint64_t rt_global_buffer_ptr;
236256
//};
237257

238258
// For SIMD8:
@@ -259,46 +279,6 @@ void WIFuncResolution::visitCallInst(CallInst& CI)
259279
// uint16_t lz[32];
260280
//};
261281

262-
263-
class GLOBAL_STATE_FIELD_OFFSETS
264-
{
265-
public:
266-
// This class holds offsets of various fields in side buffer
267-
static const uint32_t STRUCT_SIZE = 0;
268-
269-
static const uint32_t VERSION = STRUCT_SIZE + sizeof(uint8_t);
270-
271-
static const uint32_t NUM_WORK_DIM = VERSION + sizeof(uint8_t);
272-
273-
static const uint32_t SIMDSIZE = NUM_WORK_DIM + sizeof(uint8_t);
274-
275-
static const uint32_t LOCAL_SIZES = SIMDSIZE + sizeof(uint8_t);
276-
static const uint32_t LOCAL_SIZE_X = LOCAL_SIZES;
277-
static const uint32_t LOCAL_SIZE_Y = LOCAL_SIZE_X + sizeof(uint32_t);
278-
static const uint32_t LOCAL_SIZE_Z = LOCAL_SIZE_Y + sizeof(uint32_t);
279-
280-
static const uint32_t GLOBAL_SIZES = LOCAL_SIZE_Z + sizeof(uint32_t);
281-
static const uint32_t GLOBAL_SIZE_X = GLOBAL_SIZES;
282-
static const uint32_t GLOBAL_SIZE_Y = GLOBAL_SIZE_X + sizeof(uint64_t);
283-
static const uint32_t GLOBAL_SIZE_Z = GLOBAL_SIZE_Y + sizeof(uint64_t);
284-
285-
static const uint32_t PRINTF_BUFFER = GLOBAL_SIZE_Z + sizeof(uint64_t);
286-
287-
static const uint32_t GLOBAL_OFFSETS = PRINTF_BUFFER + sizeof(uint64_t);
288-
static const uint32_t GLOBAL_OFFSET_X = GLOBAL_OFFSETS;
289-
static const uint32_t GLOBAL_OFFSET_Y = GLOBAL_OFFSET_X + sizeof(uint64_t);
290-
static const uint32_t GLOBAL_OFFSET_Z = GLOBAL_OFFSET_Y + sizeof(uint64_t);
291-
292-
static const uint32_t LOCAL_IDS = GLOBAL_OFFSET_Z + sizeof(uint64_t);
293-
294-
static const uint32_t GROUP_COUNTS = LOCAL_IDS + sizeof(uint64_t);
295-
static const uint32_t GROUP_COUNT_X = GROUP_COUNTS;
296-
static const uint32_t GROUP_COUNT_Y = GROUP_COUNT_X + sizeof(uint32_t);
297-
static const uint32_t GROUP_COUNT_Z = GROUP_COUNT_Y + sizeof(uint32_t);
298-
299-
static const uint32_t TOTAL_SIZE = GROUP_COUNT_Z + sizeof(uint32_t);
300-
};
301-
302282
llvm::Value* LowerImplicitArgIntrinsics::BuildLoadInst(llvm::CallInst& CI, unsigned int Offset, llvm::Type* DataType)
303283
{
304284
// This function computes type aligned address that includes Offset.
@@ -357,9 +337,9 @@ llvm::Value* LowerImplicitArgIntrinsics::BuildLoadInst(llvm::CallInst& CI, unsig
357337

358338
if (Offset != AlignedOffset)
359339
{
360-
auto ByteType = Type::getInt8Ty(Builder.getContext());
361-
auto BitCastToByte = Builder.CreateBitCast(LoadedData, ByteType);
362-
Value* NewVector = UndefValue::get(IGCLLVM::FixedVectorType::get(ByteType, Size));
340+
auto ByteVectorType = IGCLLVM::FixedVectorType::get(Builder.getInt8Ty(), LoadByteSize);
341+
auto BitCastToByte = Builder.CreateBitCast(LoadedData, ByteVectorType);
342+
Value* NewVector = UndefValue::get(IGCLLVM::FixedVectorType::get(Builder.getInt8Ty(), Size));
363343
for (unsigned int I = Offset; I != (Offset + Size); ++I)
364344
{
365345
auto Elem = Builder.CreateExtractElement(BitCastToByte, I - AlignedOffset);
@@ -790,7 +770,7 @@ void LowerImplicitArgIntrinsics::visitCallInst(CallInst& CI)
790770

791771
// Get Local ID Base Ptr
792772
auto DataTypeI64 = Type::getInt64Ty(F->getParent()->getContext());
793-
unsigned int Offset = GLOBAL_STATE_FIELD_OFFSETS::LOCAL_IDS;
773+
unsigned int Offset = offsetof(implicit_args, local_id_table_ptr);
794774
auto LocalIDBase = BuildLoadInst(CI, Offset, DataTypeI64);
795775

796776
// Get local thread id
@@ -842,7 +822,7 @@ void LowerImplicitArgIntrinsics::visitCallInst(CallInst& CI)
842822
// Assume local size and enqueued local size are the same
843823
auto ElemTypeD = Type::getInt32Ty(F->getParent()->getContext());
844824
auto VecTyD = IGCLLVM::FixedVectorType::get(ElemTypeD, 3);
845-
unsigned int Offset = GLOBAL_STATE_FIELD_OFFSETS::LOCAL_SIZE_X;
825+
unsigned int Offset = offsetof(implicit_args, local_size_x);
846826
auto LoadInst = BuildLoadInst(CI, Offset, VecTyD);
847827
V = LoadInst;
848828
break;
@@ -851,7 +831,7 @@ void LowerImplicitArgIntrinsics::visitCallInst(CallInst& CI)
851831
{
852832
// global_offset is loaded from PayloadHeader[0:2]
853833
// currently there are no other uses for payload header.
854-
unsigned int Offset = GLOBAL_STATE_FIELD_OFFSETS::GLOBAL_OFFSET_X;
834+
unsigned int Offset = offsetof(implicit_args, global_offset_x);
855835
auto ElemTypeD = Type::getInt32Ty(F->getParent()->getContext());
856836
auto VecTyQ = IGCLLVM::FixedVectorType::get(Type::getInt64Ty(F->getParent()->getContext()), 3);
857837
auto LoadInst = BuildLoadInst(CI, Offset, VecTyQ);
@@ -868,7 +848,7 @@ void LowerImplicitArgIntrinsics::visitCallInst(CallInst& CI)
868848
case GenISAIntrinsic::GenISA_getGlobalSize:
869849
case GenISAIntrinsic::GenISA_getStageInGridSize:
870850
{
871-
unsigned int Offset = GLOBAL_STATE_FIELD_OFFSETS::GLOBAL_SIZE_X;
851+
unsigned int Offset = offsetof(implicit_args, global_size_x);
872852
auto VecTyQ = IGCLLVM::FixedVectorType::get(Type::getInt64Ty(F->getParent()->getContext()), 3);
873853
auto ElemTypeD = Type::getInt32Ty(F->getParent()->getContext());
874854
auto LoadInst = BuildLoadInst(CI, Offset, VecTyQ);
@@ -886,15 +866,15 @@ void LowerImplicitArgIntrinsics::visitCallInst(CallInst& CI)
886866
{
887867
auto ElemTypeUD = Type::getInt32Ty(F->getParent()->getContext());
888868
auto VecTyUD = IGCLLVM::FixedVectorType::get(ElemTypeUD, 3);
889-
unsigned int Offset = GLOBAL_STATE_FIELD_OFFSETS::GROUP_COUNT_X;
869+
unsigned int Offset = offsetof(implicit_args, group_count_x);
890870
auto LoadInst = BuildLoadInst(CI, Offset, VecTyUD);
891871
V = LoadInst;
892872
break;
893873
}
894874
case GenISAIntrinsic::GenISA_getWorkDim:
895875
{
896876
unsigned int Size = 4;
897-
unsigned int Offset = GLOBAL_STATE_FIELD_OFFSETS::NUM_WORK_DIM / Size;
877+
unsigned int Offset = offsetof(implicit_args, num_work_dim) / Size;
898878
auto TypeUD = Type::getInt32Ty(F->getParent()->getContext());
899879
auto LoadInst = BuildLoadInst(CI, Offset, TypeUD);
900880
auto LShr = Builder.CreateLShr(LoadInst, (uint64_t)16);
@@ -906,12 +886,20 @@ void LowerImplicitArgIntrinsics::visitCallInst(CallInst& CI)
906886
{
907887
// This function is invoked when expanding printf call to retrieve printf buffer ptr.
908888
auto DataTypeI64 = Type::getInt64Ty(CI.getFunction()->getParent()->getContext());
909-
unsigned int Offset = GLOBAL_STATE_FIELD_OFFSETS::PRINTF_BUFFER;
889+
unsigned int Offset = offsetof(implicit_args, printf_buffer_ptr);
910890
auto Result = BuildLoadInst(CI, Offset, DataTypeI64);
911891
Result = Builder.CreateIntToPtr(Result, CI.getType());
912892
V = Result;
913893
break;
914894
}
895+
case GenISAIntrinsic::GenISA_getRtGlobalBufferPtr:
896+
{
897+
unsigned int Offset = offsetof(implicit_args, rt_global_buffer_ptr);
898+
auto Result = BuildLoadInst(CI, Offset, Builder.getInt64Ty());
899+
Result = Builder.CreateIntToPtr(Result, CI.getType());
900+
V = Result;
901+
break;
902+
}
915903
default:
916904
break;
917905
}

‎IGC/Compiler/Optimizer/OpenCLPasses/WIFuncs/implicit_args_struct.h

Lines changed: 27 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,27 @@
1+
#ifndef IMPLICIT_ARGS_STRUCT_H_
2+
#define IMPLICIT_ARGS_STRUCT_H_
3+
4+
struct implicit_args {
5+
uint8_t struct_size;
6+
uint8_t struct_version;
7+
uint8_t num_work_dim;
8+
uint8_t simd_width;
9+
uint32_t local_size_x;
10+
uint32_t local_size_y;
11+
uint32_t local_size_z;
12+
uint64_t global_size_x;
13+
uint64_t global_size_y;
14+
uint64_t global_size_z;
15+
uint64_t printf_buffer_ptr;
16+
uint64_t global_offset_x;
17+
uint64_t global_offset_y;
18+
uint64_t global_offset_z;
19+
uint64_t local_id_table_ptr;
20+
uint32_t group_count_x;
21+
uint32_t group_count_y;
22+
uint32_t group_count_z;
23+
uint32_t padding0;
24+
uint64_t rt_global_buffer_ptr;
25+
};
26+
27+
#endif // IMPLICIT_ARGS_STRUCT_H_

‎IGC/GenISAIntrinsics/Intrinsic_definitions.py

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1231,6 +1231,11 @@
12311231
[],
12321232
"None"]],
12331233
####################################################################################################
1234+
"GenISA_getRtGlobalBufferPtr": ["",
1235+
[("anyptr", "result"),
1236+
[],
1237+
"None"]],
1238+
####################################################################################################
12341239
"GenISA_getSR0": ["sr0.# the state register",
12351240
[("int", "result"),
12361241
[("int", "index/offset of the subregister within sr0")],

‎IGC/ZEBinWriter/zebin/source/autogen/ZEInfo.hpp

Lines changed: 3 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
/*========================== begin_copyright_notice ============================
22
3-
Copyright (C) 2020-2022 Intel Corporation
3+
Copyright (C) 2020-2023 Intel Corporation
44
55
SPDX-License-Identifier: MIT
66
@@ -45,7 +45,7 @@ struct zeInfoExecutionEnv
4545
{
4646
bool operator==(const zeInfoExecutionEnv& other) const
4747
{
48-
return barrier_count == other.barrier_count && disable_mid_thread_preemption == other.disable_mid_thread_preemption && grf_count == other.grf_count && has_4gb_buffers == other.has_4gb_buffers && has_device_enqueue == other.has_device_enqueue && has_dpas == other.has_dpas && has_fence_for_image_access == other.has_fence_for_image_access && has_global_atomics == other.has_global_atomics && has_multi_scratch_spaces == other.has_multi_scratch_spaces && has_no_stateless_write == other.has_no_stateless_write && has_stack_calls == other.has_stack_calls && require_disable_eufusion == other.require_disable_eufusion && indirect_stateless_count == other.indirect_stateless_count && inline_data_payload_size == other.inline_data_payload_size && offset_to_skip_per_thread_data_load == other.offset_to_skip_per_thread_data_load && offset_to_skip_set_ffid_gp == other.offset_to_skip_set_ffid_gp && required_sub_group_size == other.required_sub_group_size && required_work_group_size == other.required_work_group_size && simd_size == other.simd_size && slm_size == other.slm_size && subgroup_independent_forward_progress == other.subgroup_independent_forward_progress && thread_scheduling_mode == other.thread_scheduling_mode && work_group_walk_order_dimensions == other.work_group_walk_order_dimensions && eu_thread_count == other.eu_thread_count && has_sample == other.has_sample;
48+
return barrier_count == other.barrier_count && disable_mid_thread_preemption == other.disable_mid_thread_preemption && grf_count == other.grf_count && has_4gb_buffers == other.has_4gb_buffers && has_device_enqueue == other.has_device_enqueue && has_dpas == other.has_dpas && has_fence_for_image_access == other.has_fence_for_image_access && has_global_atomics == other.has_global_atomics && has_multi_scratch_spaces == other.has_multi_scratch_spaces && has_no_stateless_write == other.has_no_stateless_write && has_stack_calls == other.has_stack_calls && require_disable_eufusion == other.require_disable_eufusion && indirect_stateless_count == other.indirect_stateless_count && inline_data_payload_size == other.inline_data_payload_size && offset_to_skip_per_thread_data_load == other.offset_to_skip_per_thread_data_load && offset_to_skip_set_ffid_gp == other.offset_to_skip_set_ffid_gp && required_sub_group_size == other.required_sub_group_size && required_work_group_size == other.required_work_group_size && simd_size == other.simd_size && slm_size == other.slm_size && subgroup_independent_forward_progress == other.subgroup_independent_forward_progress && thread_scheduling_mode == other.thread_scheduling_mode && work_group_walk_order_dimensions == other.work_group_walk_order_dimensions && eu_thread_count == other.eu_thread_count && has_sample == other.has_sample && has_rtcalls == other.has_rtcalls;
4949
}
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zeinfo_int32_t barrier_count = 0;
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zeinfo_bool_t disable_mid_thread_preemption = false;
@@ -72,6 +72,7 @@ struct zeInfoExecutionEnv
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std::vector<zeinfo_int32_t> work_group_walk_order_dimensions;
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zeinfo_int32_t eu_thread_count = 0;
7474
zeinfo_bool_t has_sample = false;
75+
zeinfo_bool_t has_rtcalls = false;
7576
};
7677
struct zeInfoPayloadArgument
7778
{

‎IGC/ZEBinWriter/zebin/source/autogen/ZEInfoYAML.cpp

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
/*========================== begin_copyright_notice ============================
22
3-
Copyright (C) 2020-2022 Intel Corporation
3+
Copyright (C) 2020-2023 Intel Corporation
44
55
SPDX-License-Identifier: MIT
66
@@ -81,6 +81,7 @@ void MappingTraits<zeInfoExecutionEnv>::mapping(IO& io, zeInfoExecutionEnv& info
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io.mapOptional("work_group_walk_order_dimensions", info.work_group_walk_order_dimensions);
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io.mapRequired("eu_thread_count", info.eu_thread_count);
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io.mapOptional("has_sample", info.has_sample, false);
84+
io.mapOptional("has_rtcalls", info.has_rtcalls, false);
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}
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void MappingTraits<zeInfoPayloadArgument>::mapping(IO& io, zeInfoPayloadArgument& info)
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{

‎IGC/ZEBinWriter/zebin/source/autogen/ZEInfoYAML.hpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
/*========================== begin_copyright_notice ============================
22
3-
Copyright (C) 2020-2022 Intel Corporation
3+
Copyright (C) 2020-2023 Intel Corporation
44
55
SPDX-License-Identifier: MIT
66

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