Fixed warning from statical code analizer

.

Author: igorban-intel

IGC/VectorCompiler/lib/GenXCodeGen/GenXCisaBuilder.cpp

@@ -3164,8 +3164,9 @@ void GenXKernelBuilder::buildGoto(CallInst *Goto, BranchInst *Branch) {
     IGC_ASSERT(PredReg->Category == vc::RegCategory::Predicate);
   }
 
-  uint8_t execSize = genx::log2(
+  auto execSize = genx::log2(
       cast<IGCLLVM::FixedVectorType>(Pred->getType())->getNumElements());
+  IGC_ASSERT_EXIT(execSize > 0);
 
   // Visa decoder part
   VISA_EMask_Ctrl emask = VISA_EMask_Ctrl((execSize >> 0x4) & 0xF);
@@ -5221,15 +5222,15 @@ GenXKernelBuilder::createGeneralOperand(Region *R, VISA_GenVar *Decl,
   // Write the vISA general operand, canonicalizing the
   // region parameters where applicable.
   IGC_ASSERT_MESSAGE(Decl, "no register allocated for this value");
+  IGC_ASSERT_EXIT(GrfByteSize > 0);
+  auto Off = R->Offset >> genx::log2(GrfByteSize);
+  auto NumOff = (R->Offset & (GrfByteSize - 1)) / R->ElementBytes;
   if (!IsDest) {
-    ResultOperand = createCisaSrcOperand(
-        Decl, static_cast<VISA_Modifier>(Mod), R->VStride, R->Width, R->Stride,
-        R->Offset >> genx::log2(GrfByteSize),
-        (R->Offset & (GrfByteSize - 1)) / R->ElementBytes);
+    ResultOperand =
+        createCisaSrcOperand(Decl, static_cast<VISA_Modifier>(Mod), R->VStride,
+                             R->Width, R->Stride, Off, NumOff);
   } else {
-    ResultOperand = createCisaDstOperand(
-        Decl, R->getDstStride(), R->Offset >> genx::log2(GrfByteSize),
-        (R->Offset & (GrfByteSize - 1)) / R->ElementBytes);
+    ResultOperand = createCisaDstOperand(Decl, R->getDstStride(), Off, NumOff);
   }
   return ResultOperand;
 }

IGC/VectorCompiler/lib/GenXCodeGen/GenXLiveElements.h

@@ -56,7 +56,7 @@ class LiveElements {
   LiveElements(Type *Ty, bool IsLive = false);
   LiveElements(const ArrayRef<SmallBitVector> LE)
       : LiveElems(LE.begin(), LE.end()) {}
-  LiveElements(SmallBitVector &&LE) : LiveElems({LE}) {}
+  LiveElements(SmallBitVector &&LE) : LiveElems({std::move(LE)}) {}
   LiveElements(const SmallBitVector &LE) = delete;
   LiveElements &operator=(const SmallBitVector &) = delete;
 

IGC/VectorCompiler/lib/GenXCodeGen/GenXLowering.cpp

@@ -1886,17 +1886,16 @@ bool GenXLowering::processInst(Instruction *Inst) {
       IntrinsicID = vc::getAnyIntrinsicID(Callee);
       IGC_ASSERT(IGCLLVM::getNumArgOperands(CI) < GenXIntrinsicInfo::OPNDMASK);
     }
-    if (ST) {
-      // use gather/scatter to implement SLM oword load/store on
-      // legacy platforms
-      if (!ST->hasSLMOWord()) {
-        if (translateSLMOWord(CI, IntrinsicID))
-          return true;
-      }
-      if (ST->getGRFByteSize() > 32) {
-        if (widenSIMD8GatherScatter(CI, IntrinsicID))
-          return true;
-      }
+    IGC_ASSERT_EXIT(ST);
+    // use gather/scatter to implement SLM oword load/store on
+    // legacy platforms
+    if (!ST->hasSLMOWord()) {
+      if (translateSLMOWord(CI, IntrinsicID))
+        return true;
+    }
+    if (ST->getGRFByteSize() > 32) {
+      if (widenSIMD8GatherScatter(CI, IntrinsicID))
+        return true;
     }
     // split gather/scatter/atomic into the width legal to the target
     if (splitGatherScatter(CI, IntrinsicID))

IGC/VectorCompiler/lib/GenXCodeGen/GenXRegionUtils.cpp

@@ -189,10 +189,10 @@ Region genx::makeRegionFromBaleInfo(const Instruction *Inst, const BaleInfo &BI,
           Result.Mask = 0;
       break;
     default:
-      IGC_ASSERT(0);
+      IGC_ASSERT_EXIT(0);
   }
   // Get the region parameters.
-  IGC_ASSERT(Subregion);
+  IGC_ASSERT_EXIT(Subregion);
   Result.ElementTy = Subregion->getType();
   if (auto *VT = dyn_cast<IGCLLVM::FixedVectorType>(Result.ElementTy)) {
     Result.ElementTy = VT->getElementType();
@@ -365,12 +365,13 @@ unsigned genx::getLegalRegionSizeForTarget(const GenXSubtarget &ST,
         // 4. no more than 8 elements in multi indirect (because there
         //    are only 8 elements in an address register).
         IGC_ASSERT_EXIT(Width > 0 && R.ElementBytes > 0);
-        unsigned LogWidth = genx::log2(Width);
+        auto LogWidth = genx::log2(Width);
         if (1U << LogWidth == Width)
           LogWidth = genx::log2(R.NumElements); // legal width
         unsigned LogElementBytes = genx::log2(R.ElementBytes);
         if (LogWidth + LogElementBytes > (LogGRFWidth + 1))
           LogWidth = LogGRFWidth + 1 - LogElementBytes;
+        IGC_ASSERT_EXIT(LogWidth >= 0);
         ValidWidth = 1 << LogWidth;
         if (ValidWidth > 8)
           ValidWidth = 8;
@@ -496,6 +497,7 @@ unsigned genx::getLegalRegionSizeForTarget(const GenXSubtarget &ST,
                 NumRows = (R.NumElements - Idx) / R.Width;
             }
           }
+          IGC_ASSERT_EXIT(NumRows > 0);
           ValidWidth = (1 << genx::log2(NumRows)) * R.Width;
         }
         if (ValidWidth == 1 && Idx % R.Width) {

IGC/VectorCompiler/lib/GenXOpts/CMTrans/CMImpParam.cpp

@@ -721,13 +721,15 @@ static Value &loadArgFromIABuffer(unsigned IID, Value &ImplArgsBufferPtr,
     IGC_ASSERT_EXIT_MESSAGE(
         0, "IA buffer is supported only for OCL/L0 so local.id "
            "must have been already transformed into local.id16");
+    return ImplArgsBufferPtr;
   case GenXIntrinsic::genx_get_scoreboard_deltas:
   case GenXIntrinsic::genx_get_scoreboard_bti:
   case GenXIntrinsic::genx_get_scoreboard_depcnt:
     // It is an assertion since the diagnostic must have been happen before.
     IGC_ASSERT_EXIT_MESSAGE(
         0, "IA buffer is supported only for OCL/L0, scoreboard "
            "builtins should not appear for those runtimes");
+    return ImplArgsBufferPtr;
   case GenXIntrinsic::genx_local_size:
     return loadVec3ArgFromIABuffer<GenXIntrinsic::genx_local_size>(
         ImplArgsBufferPtr, IRB);