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tbujewsksys_zuul
tbujewsk
authored and
sys_zuul
committed
Int64b support refactoring.
Change-Id: I862290ea42149269cd7602ba51701fe205fc93a0
1 parent 12bc1a5 commit c129ab8

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4 files changed

+34
-23
lines changed

4 files changed

+34
-23
lines changed

‎IGC/Compiler/CISACodeGen/EmitVISAPass.cpp

Lines changed: 21 additions & 21 deletions
Original file line numberDiff line numberDiff line change
@@ -2647,7 +2647,7 @@ void EmitPass::emitCmpSADs(llvm::GenIntrinsicInst* inst)
26472647
m_encoder->Push();
26482648

26492649
// Collect the MVs
2650-
if (m_currShader->m_Platform->hasNoInt64Inst()) {
2650+
if (m_currShader->m_Platform->hasNoFullI64Support()) {
26512651
CVariable* pMVMinAlias = m_currShader->GetNewAlias(pMVMin, ISA_TYPE_UD, 0, 32);
26522652
CVariable* pMVCurrAlias = m_currShader->GetNewAlias(pMVCurr, ISA_TYPE_UD, 0, 32);
26532653

@@ -5267,7 +5267,7 @@ void EmitPass::emitLegacySimdBlockWrite(llvm::Instruction* inst, llvm::Value* pt
52675267
activelanes, eOffset->GetType(), eOffset->GetAlign(), true, "ScatterOff");
52685268

52695269
CVariable* immVar = m_currShader->ImmToVariable(0x40, ISA_TYPE_UV);
5270-
if (useA64 && m_currShader->m_Platform->hasNoInt64Inst()) {
5270+
if (useA64 && m_currShader->m_Platform->hasNoInt64AddInst()) {
52715271
emitAddPair(ScatterOff, eOffset, immVar);
52725272
}
52735273
else {
@@ -5329,7 +5329,7 @@ void EmitPass::emitLegacySimdBlockWrite(llvm::Instruction* inst, llvm::Value* pt
53295329

53305330
if (bytesRemaining)
53315331
{
5332-
if (m_currShader->m_Platform->hasNoInt64Inst()) {
5332+
if (m_currShader->m_Platform->hasNoInt64AddInst()) {
53335333
CVariable* ImmVar = m_currShader->ImmToVariable(bytesToRead, ISA_TYPE_UD);
53345334
emitAddPair(pTempVar, pTempVar, ImmVar);
53355335
}
@@ -5463,7 +5463,7 @@ void EmitPass::emitLegacySimdBlockRead(llvm::Instruction* inst, llvm::Value* ptr
54635463
activelanes, eOffset->GetType(), eOffset->GetAlign(), true, "GatherOff");
54645464

54655465
CVariable* immVar = m_currShader->ImmToVariable(0x40, ISA_TYPE_UV);
5466-
if (useA64 && m_currShader->m_Platform->hasNoInt64Inst()) {
5466+
if (useA64 && m_currShader->m_Platform->hasNoInt64AddInst()) {
54675467
emitAddPair(gatherOff, eOffset, immVar);
54685468
}
54695469
else {
@@ -5524,7 +5524,7 @@ void EmitPass::emitLegacySimdBlockRead(llvm::Instruction* inst, llvm::Value* ptr
55245524

55255525
if (bytesRemaining)
55265526
{
5527-
if (m_currShader->m_Platform->hasNoInt64Inst()) {
5527+
if (m_currShader->m_Platform->hasNoInt64AddInst()) {
55285528
CVariable* ImmVar = m_currShader->ImmToVariable(bytesToRead, ISA_TYPE_UD);
55295529
emitAddPair(pTempVar, pTempVar, ImmVar);
55305530
}
@@ -8836,7 +8836,7 @@ void EmitPass::emitAddrSpaceCast(llvm::AddrSpaceCastInst* addrSpaceCast)
88368836

88378837
if (sourceAddrSpace == ADDRESS_SPACE_PRIVATE)
88388838
{
8839-
if (m_pCtx->m_hasEmu64BitInsts && m_currShader->m_Platform->hasNoInt64Inst())
8839+
if (m_pCtx->m_hasEmu64BitInsts && m_currShader->m_Platform->hasNoFullI64Support())
88408840
{
88418841
if (m_currShader->GetContext()->getRegisterPointerSizeInBits(sourceAddrSpace) == 32)
88428842
{
@@ -8907,7 +8907,7 @@ void EmitPass::emitAddrSpaceCast(llvm::AddrSpaceCastInst* addrSpaceCast)
89078907
}
89088908
else if (sourceAddrSpace == ADDRESS_SPACE_LOCAL)
89098909
{
8910-
if (m_pCtx->m_hasEmu64BitInsts && m_currShader->m_Platform->hasNoInt64Inst())
8910+
if (m_pCtx->m_hasEmu64BitInsts && m_currShader->m_Platform->hasNoFullI64Support())
89118911
{
89128912
if (m_currShader->GetContext()->getRegisterPointerSizeInBits(sourceAddrSpace) == 32)
89138913
{
@@ -8989,7 +8989,7 @@ void EmitPass::emitAddrSpaceCast(llvm::AddrSpaceCastInst* addrSpaceCast)
89898989
// Address space cast is in the form of generic -> {private, local, global}
89908990
// Tag is removed according to the address space of the destination
89918991

8992-
if (m_pCtx->m_hasEmu64BitInsts && m_currShader->m_Platform->hasNoInt64Inst())
8992+
if (m_pCtx->m_hasEmu64BitInsts && m_currShader->m_Platform->hasNoFullI64Support())
89938993
{
89948994
if (m_currShader->GetContext()->getRegisterPointerSizeInBits(destAddrSpace) == 32)
89958995
{
@@ -9075,7 +9075,7 @@ CVariable* EmitPass::createAddressSpaceTag(CVariable* src, unsigned int addrSpac
90759075
CVariable* taggedSrc = nullptr;
90769076
if (addrSpace == ADDRESS_SPACE_PRIVATE)
90779077
{
9078-
if (m_pCtx->m_hasEmu64BitInsts && m_currShader->m_Platform->hasNoInt64Inst())
9078+
if (m_pCtx->m_hasEmu64BitInsts && m_currShader->m_Platform->hasNoFullI64Support())
90799079
{
90809080
if (m_currShader->GetContext()->getRegisterPointerSizeInBits(addrSpace) == 32)
90819081
{
@@ -9145,7 +9145,7 @@ CVariable* EmitPass::createAddressSpaceTag(CVariable* src, unsigned int addrSpac
91459145
}
91469146
else if (addrSpace == ADDRESS_SPACE_LOCAL)
91479147
{
9148-
if (m_pCtx->m_hasEmu64BitInsts && m_currShader->m_Platform->hasNoInt64Inst())
9148+
if (m_pCtx->m_hasEmu64BitInsts && m_currShader->m_Platform->hasNoFullI64Support())
91499149
{
91509150
if (m_currShader->GetContext()->getRegisterPointerSizeInBits(addrSpace) == 32)
91519151
{
@@ -11015,7 +11015,7 @@ CVariable* EmitPass::BroadcastIfUniform(CVariable* pVar)
1101511015
{
1101611016
IGC_ASSERT_MESSAGE(nullptr != pVar, "pVar is null");
1101711017
VISA_Type VarT = pVar->GetType();
11018-
bool Need64BitEmu = m_currShader->m_Platform->hasNoInt64Inst() &&
11018+
bool Need64BitEmu = m_currShader->m_Platform->hasNoFullI64Support() &&
1101911019
(VarT == ISA_TYPE_Q || VarT == ISA_TYPE_UQ);
1102011020
bool IsImm = pVar->IsImmediate();
1102111021
if (pVar->IsUniform())
@@ -11882,7 +11882,7 @@ void EmitPass::emitReductionClustered(const e_opcode op, const uint64_t identity
1188211882
IGC_ASSERT_MESSAGE(iSTD::BitCount(clusterSize) == 1, "Cluster size must be a power of two.");
1188311883
IGC_ASSERT_MESSAGE(!is64bitType || CEncoder::GetCISADataTypeSize(type) == 8, "Unsupported 64-bit type.");
1188411884

11885-
IGC_ASSERT_MESSAGE(!isInt64Type || !m_currShader->m_Platform->hasNoInt64Inst(), "Int64 emulation is not supported.");
11885+
IGC_ASSERT_MESSAGE(!isInt64Type || !m_currShader->m_Platform->hasNoFullI64Support(), "Int64 emulation is not supported.");
1188611886
IGC_ASSERT_MESSAGE(!isFP64Type || !m_currShader->m_Platform->hasNoFP64Inst(), "FP64 emulation is not supported.");
1188711887
// Src might be uniform, as its value will be broadcasted during src preparation.
1188811888
// Dst uniformness depends on actual support in WIAnalysis, so far implemented for 32-clusters only.
@@ -15208,7 +15208,7 @@ void EmitPass::emitVectorLoad(LoadInst* inst, Value* offset, ConstantInt* immOff
1520815208
// on platform that does not support 64bit integer add.
1520915209
//Note: it doesn't seem to be necessary to check hasNoFP64Inst() here.
1521015210
if (srcUniform && (totalBytes == 4 || totalBytes == 8 || totalBytes == 12 || totalBytes == 16 ||
15211-
(totalBytes == 32 && (useA32 || !m_currShader->m_Platform->hasNoInt64Inst()))))
15211+
(totalBytes == 32 && (useA32 || !m_currShader->m_Platform->hasNoFullI64Support()))))
1521215212
{
1521315213
bool needTemp = !destUniform ||
1521415214
!IsGRFAligned(m_destination, EALIGN_GRF) ||
@@ -15294,7 +15294,7 @@ void EmitPass::emitVectorLoad(LoadInst* inst, Value* offset, ConstantInt* immOff
1529415294
}
1529515295

1529615296
CVariable* immVar = m_currShader->ImmToVariable(incImm, ISA_TYPE_UV);
15297-
if (!useA32 && m_currShader->m_Platform->hasNoInt64Inst()) {
15297+
if (!useA32 && m_currShader->m_Platform->hasNoInt64AddInst()) {
1529815298
emitAddPair(gatherOff, eOffset, immVar);
1529915299
}
1530015300
else {
@@ -15375,7 +15375,7 @@ void EmitPass::emitVectorLoad(LoadInst* inst, Value* offset, ConstantInt* immOff
1537515375
// Calculate the new element offset
1537615376
rawAddrVar = m_currShader->GetNewVariable(eOffset);
1537715377
CVariable* ImmVar = m_currShader->ImmToVariable(eltOffBytes, ISA_TYPE_UD);
15378-
if (!useA32 && m_currShader->m_Platform->hasNoInt64Inst()) {
15378+
if (!useA32 && m_currShader->m_Platform->hasNoInt64AddInst()) {
1537915379
emitAddPair(rawAddrVar, eOffset, ImmVar);
1538015380
}
1538115381
else {
@@ -15448,7 +15448,7 @@ void EmitPass::emitVectorLoad(LoadInst* inst, Value* offset, ConstantInt* immOff
1544815448
// Calculate the new element offset
1544915449
rawAddrVar = m_currShader->GetNewVariable(eOffset);
1545015450
CVariable* ImmVar = m_currShader->ImmToVariable(VecMessInfo.insts[i].startByte, ISA_TYPE_UD);
15451-
if (!useA32 && m_currShader->m_Platform->hasNoInt64Inst()) {
15451+
if (!useA32 && m_currShader->m_Platform->hasNoInt64AddInst()) {
1545215452
emitAddPair(rawAddrVar, eOffset, ImmVar);
1545315453
}
1545415454
else {
@@ -15608,7 +15608,7 @@ void EmitPass::emitVectorStore(StoreInst* inst, Value* offset, ConstantInt* immO
1560815608
// When work-around of A64 SKL Si limitation of SIMD4, we use SIMD8 (nbelts > nbeltsWanted)
1560915609
// in which all upper four channels are zero, meaning eOffset[0], Later, stored value
1561015610
// must use storvedVar[0] for those extra lanes.
15611-
if (!useA32 && m_currShader->m_Platform->hasNoInt64Inst()) {
15611+
if (!useA32 && m_currShader->m_Platform->hasNoInt64AddInst()) {
1561215612
emitAddPair(NewOff, eOffset, immVar);
1561315613
}
1561415614
else {
@@ -15767,7 +15767,7 @@ void EmitPass::emitVectorStore(StoreInst* inst, Value* offset, ConstantInt* immO
1576715767
// Calculate the new element offset
1576815768
rawAddrVar = m_currShader->GetNewVariable(eOffset);
1576915769
CVariable* ImmVar = m_currShader->ImmToVariable(VecMessInfo.insts[i].startByte, ISA_TYPE_UD);
15770-
if (!useA32 && m_currShader->m_Platform->hasNoInt64Inst()) {
15770+
if (!useA32 && m_currShader->m_Platform->hasNoInt64AddInst()) {
1577115771
emitAddPair(rawAddrVar, eOffset, ImmVar);
1577215772
}
1577315773
else {
@@ -15913,7 +15913,7 @@ CVariable* EmitPass::prepareAddressForUniform(
1591315913
CVariable* offHi = m_currShader->GetNewAlias(off, off->GetType(), 0, halfNElts);
1591415914
CVariable* offLo = m_currShader->GetNewAlias(off, off->GetType(), bytes2, halfNElts);
1591515915

15916-
if (isA64 && m_currShader->m_Platform->hasNoInt64Inst())
15916+
if (isA64 && m_currShader->m_Platform->hasNoInt64AddInst())
1591715917
{
1591815918
emitAddPair(newVarHi, AddrVar, offHi);
1591915919
emitAddPair(newVarLo, AddrVar, offLo);
@@ -15936,7 +15936,7 @@ CVariable* EmitPass::prepareAddressForUniform(
1593615936
m_encoder->Push();
1593715937
}
1593815938
}
15939-
else if (isA64 && m_currShader->m_Platform->hasNoInt64Inst() && pow2NElts > 1)
15939+
else if (isA64 && m_currShader->m_Platform->hasNoInt64AddInst() && pow2NElts > 1)
1594015940
{
1594115941
emitAddPair(newVar, AddrVar, off);
1594215942
}
@@ -16197,7 +16197,7 @@ void EmitPass::emitPushFrameToStack(unsigned& pushSize)
1619716197

1619816198
void EmitPass::emitAddPointer(CVariable* Dst, CVariable* Src, CVariable* offset)
1619916199
{
16200-
if (m_currShader->m_Platform->hasNoInt64Inst() &&
16200+
if (m_currShader->m_Platform->hasNoInt64AddInst() &&
1620116201
(Dst->GetType() == ISA_TYPE_Q || Dst->GetType() == ISA_TYPE_UQ) &&
1620216202
(Src->GetType() == ISA_TYPE_Q || Src->GetType() == ISA_TYPE_UQ))
1620316203
{

‎IGC/Compiler/CISACodeGen/LowerGEPForPrivMem.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -257,7 +257,7 @@ static void GetAllocaLiverange(Instruction* I, unsigned int& liverangeStart, uns
257257
bool LowerGEPForPrivMem::IsNativeType(Type* type)
258258
{
259259
if ((type->isDoubleTy() && m_ctx->platform.hasNoFP64Inst()) ||
260-
(type->isIntegerTy(64) && m_ctx->platform.hasNoInt64Inst()))
260+
(type->isIntegerTy(64) && m_ctx->platform.hasNoFullI64Support()))
261261
{
262262
return false;
263263
}

‎IGC/Compiler/CISACodeGen/Platform.hpp

Lines changed: 10 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -410,6 +410,16 @@ bool supportsSIMD16TypedRW() const
410410
return false;
411411
}
412412

413+
bool hasNoFullI64Support() const
414+
{
415+
return hasNoInt64Inst();
416+
}
417+
418+
bool hasNoInt64AddInst() const
419+
{
420+
return hasNoFullI64Support();
421+
}
422+
413423
//all the platforms which DONOT support 64 bit int operations
414424
bool hasNoInt64Inst() const {
415425
return m_platformInfo.eProductFamily == IGFX_ICELAKE_LP ||

‎IGC/Compiler/CISACodeGen/ShaderCodeGen.cpp

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -667,7 +667,8 @@ static void AddLegalizationPasses(CodeGenContext& ctx, IGCPassManager& mpm, PSSi
667667
(ctx.m_DriverInfo.Enable64BitEmu() &&
668668
(IGC_GET_FLAG_VALUE(Enable64BitEmulation) ||
669669
(IGC_GET_FLAG_VALUE(Enable64BitEmulationOnSelectedPlatform) &&
670-
ctx.platform.need64BitEmulation()))))
670+
ctx.platform.need64BitEmulation())))
671+
)
671672
{
672673
mpm.add(new BreakConstantExpr());
673674

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