Adjust BFN matching heuristics for pattern matching

VC shouldn't match non-profitable patterns. Flag register cannot be
source for BFN instruction. The finalizer emits extra MOV instructions
in such cases. So, it's better to avoid them, when the total amount of
instruction is not reduced.

We also need to reduce the use threshold for instructions folded into
the BFN. This will reduce the value live ranges and improve the
register pressure.

Author: vmustya

IGC/VectorCompiler/lib/GenXCodeGen/GenXPatternMatch.cpp

@@ -242,11 +242,11 @@ bool GenXPatternMatch::runOnFunction(Function &F) {
     Changed |= reassociateIntegerMad(&F);
   }
 
+  visit(F);
+
   if (EnableBfnMatcher && ST->hasAdd3Bfn())
     matchBFN(F);
 
-  visit(F);
-
   if (Kind == PatternMatchKind::PreLegalization) {
     Changed |= placeConstants(&F);
     Changed |= vectorizeConstants(&F);
@@ -396,7 +396,7 @@ class BfnMatcher {
   static constexpr StringRef OpNames[] = {"not", "and", "or", "xor"};
   static constexpr unsigned LutValues[] = {0xaa, 0xcc, 0xf0};
 
-  static constexpr unsigned UsesThreshold = 4;
+  static constexpr unsigned UsesThreshold = 2;
   static constexpr unsigned SourceLimit = 3;
 
 public:
@@ -411,7 +411,7 @@ class BfnMatcher {
     if (!Ty->isIntOrIntVectorTy(16) && !Ty->isIntOrIntVectorTy(32))
       return false;
 
-    unsigned MatchedOps = 0;
+    MatchedOps = 0;
     Srcs.insert(MainInst);
 
     // Grow the pattern to find the source operands using a BFS.
@@ -422,7 +422,7 @@ class BfnMatcher {
       auto *Inst = Queue.front();
       Queue.pop();
 
-      if (Inst->hasNUsesOrMore(UsesThreshold))
+      if (MatchedOps > 0 && Inst->hasNUsesOrMore(UsesThreshold))
         return false;
 
       auto Op = getOperation(Inst);
@@ -536,6 +536,11 @@ class BfnMatcher {
         SrcsOrdered[2] = NegCSrc2;
     }
 
+    if (!isProfitable()) {
+      LLVM_DEBUG(dbgs() << "BFN: Not profitable\n");
+      return false;
+    }
+
     IRBuilder<> Builder(MainInst);
 
     auto Lut = getLutValue(MainInst);
@@ -643,10 +648,30 @@ class BfnMatcher {
     return false;
   }
 
+  static bool isFlagInput(Value *V) {
+    auto *Cast = dyn_cast<BitCastInst>(V);
+    if (!Cast)
+      return false;
+
+    auto *Src = Cast->getOperand(0);
+    auto *SrcTy = Src->getType();
+    return SrcTy->isIntOrIntVectorTy(1);
+  }
+
+  bool isProfitable() const {
+    unsigned NumOfFlagInputs = llvm::count_if(SrcsOrdered, isFlagInput);
+    if (NumOfFlagInputs >= MatchedOps)
+      return false;
+
+    return true;
+  }
+
   BinaryOperator *MainInst;
   const bool TryGreedy;
   SmallSetVector<Value *, 4> Srcs;
   SmallVector<Value *, 4> SrcsOrdered;
+
+  unsigned MatchedOps = 0;
 };
 
 // Class to identify cases where a comparison and select are equivalent to a

IGC/VectorCompiler/test/PatternMatch/bfn_match.ll

@@ -108,24 +108,27 @@ define i32 @test_match_i32_combine_by_mask_const(i32 %a, i32 %b) {
   ret i32 %3
 }
 
-define i32 @test_match_i32_const_zero(i32 %a, i32 %b, i32 %mask) {
-; CHECK: ret i32 0
-  %nmask = xor i32 -1, %mask
-  %1 = and i32 %a, %mask
-  %2 = and i32 %b, %nmask
-  %3 = or i32 %1, %2
-  %4 = xor i32 %3, -1
-  %5 = and i32 %3, %4
-  ret i32 %5
+declare void @use(i32)
+
+; CHECK-LABEL: @test_unmatch_i32(
+define i32 @test_unmatch_i32(i32 %op0, i32 %op1, i32 %op2)  {
+; CHECK-NOT: call void @llvm.genx.bfn.i32.i32(
+  %1 = and i32 %op0, %op1
+  %2 = and i32 %1, %op2
+  call void @use(i32 %1)
+
+  ret i32 %2
 }
 
-define i32 @test_match_i32_const_one(i32 %a, i32 %b, i32 %mask) {
-; CHECK: ret i32 -1
-  %nmask = xor i32 -1, %mask
-  %1 = and i32 %a, %mask
-  %2 = and i32 %b, %nmask
-  %3 = or i32 %1, %2
-  %4 = xor i32 %3, -1
-  %5 = or i32 %3, %4
-  ret i32 %5
+; CHECK-LABEL: @test_unmatch_flag
+define i32 @test_unmatch_flag(<32 x i1> %a, <32 x i1> %b, <32 x i1> %c) {
+  %as = bitcast <32 x i1> %a to i32
+  %bs = bitcast <32 x i1> %b to i32
+  %cs = bitcast <32 x i1> %c to i32
+
+; CHECK-NOT: call i32 @llvm.genx.bfn.i32.i32(
+  %1 = and i32 %as, %bs
+  %2 = and i32 %bs, %cs
+
+  ret i32 %2
 }