Skip to content

Commit c7d5ab9

Browse files
scottp101igcbot
scottp101
authored and
igcbot
committed
cleanup
cleanup
1 parent 6a0d281 commit c7d5ab9

File tree

6 files changed

+4
-114
lines changed

6 files changed

+4
-114
lines changed

‎IGC/Compiler/CISACodeGen/DriverInfo.hpp

Lines changed: 0 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -325,12 +325,6 @@ namespace IGC
325325
// If enabled, IGC must provide the corresponding UMD info on how much
326326
// memory to allocate for the RTGlobals + global root signature.
327327
virtual bool supportsExpandedRTGlobals() const { return false; }
328-
// If enabled, UMD must support setting up threadgroup according to
329-
// RayTracingCustomTileXDim* and RayTracingCustomTileYDim*. If you want
330-
// to experiment with non-power-of-2 x dimensions, you also have to
331-
// support filling local IDs in the indirect state for the shader to
332-
// read (not required otherwise).
333-
virtual bool supportsRaytracingTiling() const { return false; }
334328
// Enables the use of scratch space in raytracing shaders when possible
335329
virtual bool supportsRTScratchSpace() const { return false; }
336330
// Enables Raytracing printf

‎IGC/Compiler/CISACodeGen/EmitVISAPass.cpp

Lines changed: 2 additions & 90 deletions
Original file line numberDiff line numberDiff line change
@@ -23191,9 +23191,7 @@ void EmitPass::emitInlinedDataValue(llvm::GenIntrinsicInst* I)
2319123191

2319223192
void EmitPass::emitTileXOffset(TileXIntrinsic* I)
2319323193
{
23194-
const bool UseSubtile =
23195-
(I->getSubtileXDim() != 0 && I->getSubtileYDim() != 0);
23196-
const uint32_t XDim = UseSubtile ? I->getSubtileXDim() : I->getTileXDim();
23194+
const uint32_t XDim = I->getTileXDim();
2319723195
IGC_ASSERT(iSTD::IsPowerOfTwo(XDim));
2319823196

2319923197
const uint32_t lanes = numLanes(m_currShader->m_SIMDSize);
@@ -23246,54 +23244,11 @@ void EmitPass::emitTileXOffset(TileXIntrinsic* I)
2324623244
m_encoder->Push();
2324723245
}
2324823246
}
23249-
23250-
if (UseSubtile)
23251-
{
23252-
IGC_ASSERT(I->getTileXDim() % I->getSubtileXDim() == 0);
23253-
IGC_ASSERT((I->getSubtileXDim() * I->getSubtileYDim()) % lanes == 0);
23254-
uint32_t SubtilesInRow = I->getTileXDim() / I->getSubtileXDim();
23255-
uint32_t ThreadsInSubtile =
23256-
(I->getSubtileXDim() * I->getSubtileYDim()) / lanes;
23257-
IGC_ASSERT(iSTD::IsPowerOfTwo(ThreadsInSubtile));
23258-
IGC_ASSERT(iSTD::IsPowerOfTwo(SubtilesInRow));
23259-
23260-
// subtile_linear_idx = tid / threads_in_subtile
23261-
CVariable* ShiftAmt = m_currShader->ImmToVariable(
23262-
llvm::countTrailingZeros(ThreadsInSubtile), ISA_TYPE_UW);
23263-
23264-
CVariable* SubtileLinearIdx = m_currShader->GetNewVariable(
23265-
1, ISA_TYPE_UW, EALIGN_WORD, true, "SubtileLinearIdx");
23266-
23267-
m_encoder->Shr(SubtileLinearIdx, TID, ShiftAmt);
23268-
23269-
// subtile_idx.x = subtile_linear_idx % subtiles_in_row
23270-
CVariable* Mask = m_currShader->ImmToVariable(
23271-
SubtilesInRow - 1, ISA_TYPE_UW);
23272-
23273-
CVariable* SubtileIdxX = m_currShader->GetNewVariable(
23274-
1, ISA_TYPE_UW, EALIGN_WORD, true, "SubtileIdx.x");
23275-
23276-
m_encoder->And(SubtileIdxX, SubtileLinearIdx, Mask);
23277-
23278-
// m_destination = subtile_idx.x * subtile_dim.x + m_destination
23279-
CVariable* ShiftAmt2 = m_currShader->ImmToVariable(
23280-
llvm::countTrailingZeros(I->getSubtileXDim()), ISA_TYPE_UW);
23281-
23282-
CVariable* Base = m_currShader->GetNewVariable(
23283-
1, ISA_TYPE_UW, EALIGN_WORD, true, "BaseX");
23284-
23285-
m_encoder->Shl(Base, SubtileIdxX, ShiftAmt2);
23286-
m_encoder->Add(m_destination, Base, m_destination);
23287-
23288-
m_encoder->Push();
23289-
}
2329023247
}
2329123248

2329223249
void EmitPass::emitTileYOffset(TileYIntrinsic* I)
2329323250
{
23294-
const bool UseSubtile =
23295-
(I->getSubtileXDim() != 0 && I->getSubtileYDim() != 0);
23296-
const uint32_t XDim = UseSubtile ? I->getSubtileXDim() : I->getTileXDim();
23251+
const uint32_t XDim = I->getTileXDim();
2329723252
IGC_ASSERT(iSTD::IsPowerOfTwo(XDim));
2329823253

2329923254
const uint32_t lanes = numLanes(m_currShader->m_SIMDSize);
@@ -23346,49 +23301,6 @@ void EmitPass::emitTileYOffset(TileYIntrinsic* I)
2334623301
m_encoder->Add(m_destination, YVals, Tmp);
2334723302
m_encoder->Push();
2334823303
}
23349-
23350-
if (UseSubtile)
23351-
{
23352-
// Need to wrap the initial grid first with:
23353-
// m_destination = m_destination % subtile_dim.y.
23354-
IGC_ASSERT(iSTD::IsPowerOfTwo(I->getSubtileYDim()));
23355-
23356-
CVariable* Mask = m_currShader->ImmToVariable(
23357-
I->getSubtileYDim() - 1, ISA_TYPE_UW);
23358-
m_encoder->And(m_destination, m_destination, Mask);
23359-
23360-
IGC_ASSERT(I->getTileXDim() % I->getSubtileXDim() == 0);
23361-
IGC_ASSERT((I->getSubtileXDim() * I->getSubtileYDim()) % lanes == 0);
23362-
uint32_t SubtilesInRow = I->getTileXDim() / I->getSubtileXDim();
23363-
uint32_t ThreadsInSubtile =
23364-
(I->getSubtileXDim() * I->getSubtileYDim()) / lanes;
23365-
IGC_ASSERT(iSTD::IsPowerOfTwo(ThreadsInSubtile));
23366-
IGC_ASSERT(iSTD::IsPowerOfTwo(SubtilesInRow));
23367-
23368-
uint32_t ThreadsInRow = ThreadsInSubtile * SubtilesInRow;
23369-
IGC_ASSERT(iSTD::IsPowerOfTwo(ThreadsInRow));
23370-
23371-
// subtile_idx.y = tid / threads_in_row
23372-
CVariable* ShiftAmt = m_currShader->ImmToVariable(
23373-
llvm::countTrailingZeros(ThreadsInRow), ISA_TYPE_UW);
23374-
23375-
CVariable* SubtileIdxY = m_currShader->GetNewVariable(
23376-
1, ISA_TYPE_UW, EALIGN_WORD, true, "SubtileIdx.y");
23377-
23378-
m_encoder->Shr(SubtileIdxY, TID, ShiftAmt);
23379-
23380-
// m_destination = subtile_idx.y * subtile_dim.y + m_destination
23381-
CVariable* ShiftAmt2 = m_currShader->ImmToVariable(
23382-
llvm::countTrailingZeros(I->getSubtileYDim()), ISA_TYPE_UW);
23383-
23384-
CVariable* Base = m_currShader->GetNewVariable(
23385-
1, ISA_TYPE_UW, EALIGN_WORD, true, "BaseY");
23386-
23387-
m_encoder->Shl(Base, SubtileIdxY, ShiftAmt2);
23388-
m_encoder->Add(m_destination, Base, m_destination);
23389-
23390-
m_encoder->Push();
23391-
}
2339223304
}
2339323305

2339423306
void EmitPass::emitTraceRay(TraceRayIntrinsic* I, bool RayQueryEnable)

‎IGC/Compiler/CodeGenPublic.h

Lines changed: 0 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -522,8 +522,6 @@ namespace IGC
522522
// TODO: need to separate out bindless and raygen into two structs
523523
// for both DX and Vulkan.
524524

525-
void* ThreadPayloadData = nullptr;
526-
unsigned int TotalDataLength = 0;
527525
// dynamically select between the 1D and 2D layout at runtime based
528526
// on the size of the dispatch.
529527
uint32_t DimX1D = 0;

‎IGC/GenISAIntrinsics/GenIntrinsicInst.h

Lines changed: 0 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -1535,12 +1535,6 @@ class TileIntrinsic : public GenIntrinsicInst {
15351535
uint32_t getTileXDim() const {
15361536
return (uint32_t)cast<ConstantInt>(getOperand(1))->getZExtValue();
15371537
}
1538-
uint32_t getSubtileXDim() const {
1539-
return (uint32_t)cast<ConstantInt>(getOperand(2))->getZExtValue();
1540-
}
1541-
uint32_t getSubtileYDim() const {
1542-
return (uint32_t)cast<ConstantInt>(getOperand(3))->getZExtValue();
1543-
}
15441538
};
15451539

15461540
class TileXIntrinsic : public TileIntrinsic {

‎IGC/GenISAIntrinsics/Intrinsic_definitions.py

Lines changed: 2 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -3248,17 +3248,13 @@
32483248
"GenISA_TileXOffset": ["Raytracing: returns the X-offset within a raytracing tile",
32493249
[("short", "The offset"),
32503250
[("short", "TID (r0.4:uw & 0xff)"),
3251-
("short", "X Dimension Size (Tile)"),
3252-
("short", "X Dimension Size (Subtile) (0 == no subtile)"),
3253-
("short", "Y Dimension Size (Subtile) (0 == no subtile)")],
3251+
("short", "X Dimension Size (Tile)")],
32543252
"NoMem"]],
32553253
####################################################################################################
32563254
"GenISA_TileYOffset": ["Raytracing: returns the Y-offset within a raytracing tile",
32573255
[("short", "The offset"),
32583256
[("short", "TID (r0.4:uw & 0xff)"),
3259-
("short", "X Dimension Size (Tile)"),
3260-
("short", "X Dimension Size (Subtile) (0 == no subtile)"),
3261-
("short", "Y Dimension Size (Subtile) (0 == no subtile)")],
3257+
("short", "X Dimension Size (Tile)")],
32623258
"NoMem"]],
32633259
####################################################################################################
32643260
"GenISA_SpillValue": ["Raytracing: Spill a value onto the stack",

‎IGC/common/igc_flags.h

Lines changed: 0 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -880,14 +880,10 @@ DECLARE_IGC_GROUP("Raytracing Options")
880880
DECLARE_IGC_REGKEY(bool, DisableRayTracingConstantCoalescing, false, "Disable coalescing", true)
881881
DECLARE_IGC_REGKEY(DWORD, RayTracingConstantCoalescingMinBlockSize, 4, "Set the minimum load size in # OWords = [1,2,4,8,16].", true)
882882
DECLARE_IGC_REGKEY(bool, DisableRayTracingOptimizations, false, "Disable RayTracing Optimizations for debugging", true)
883-
DECLARE_IGC_REGKEY(bool, DisableRayTracingCustomTile, false, "Disables X,Y regkeys to pick a particular tile size (i.e., workgroup dimensions)", true)
884883
DECLARE_IGC_REGKEY(DWORD, RayTracingCustomTileXDim1D, 256, "X dimension of tile (default: 256)", true)
885884
DECLARE_IGC_REGKEY(DWORD, RayTracingCustomTileYDim1D, 1, "Y dimension of tile (default: 1)", true)
886885
DECLARE_IGC_REGKEY(DWORD, RayTracingCustomTileXDim2D, 0, "X dimension of tile (default: 32)", true)
887886
DECLARE_IGC_REGKEY(DWORD, RayTracingCustomTileYDim2D, 0, "Y dimension of tile (default: 4 for XE, 32 for XE2+)", true)
888-
DECLARE_IGC_REGKEY(bool, EnableRayTracingCustomSubtile, false, "Enables X,Y regkeys to pick a particular subtile size (i.e., tile within a workgroup)", true)
889-
DECLARE_IGC_REGKEY(DWORD, RayTracingCustomSubtileXDim2D, 4, "X dimension of subtile (default: 4)", true)
890-
DECLARE_IGC_REGKEY(DWORD, RayTracingCustomSubtileYDim2D, 4, "Y dimension of subtile (default: 4)", true)
891887
DECLARE_IGC_REGKEY(bool, DisableLSCControlsForRayTracing, false, "Disable different LSC Controls for HW and SW portions of the RTStack", true)
892888
DECLARE_IGC_REGKEY(bool, ForceRTStackLoadCacheCtrl, false, "Enables RTStackLoadCacheCtrl regkey for custom lsc load cache controls in the RTStack", true)
893889
DECLARE_IGC_REGKEY_ENUM(RTStackLoadCacheCtrl, 0, "Load Cache Controls", LSC_CACHE_CTRL_OPTIONS, true)

0 commit comments

Comments
 (0)