Changes in code.

Author: pratikashar

visa/G4_Opcode.h

@@ -62,8 +62,7 @@ enum class BankAlign {
   Odd = 3,      // old align
   Even2GRF = 4, // 2-GRF even align 1100
   Odd2GRF = 5,  // 2-GRF old align, 0011
-  QuadGRF = 6,  // 4-GRF align
-  Align_NUM = 7 // Num of alignment
+  Align_NUM = 6 // Num of alignment
 };
 
 // An instruction's execution width

visa/GraphColor.cpp

@@ -2650,12 +2650,9 @@ void GlobalRA::updateSubRegAlignment(G4_SubReg_Align subAlign) {
   }
 }
 
-int GlobalRA::getAlignFromAugBucket(G4_Declare *dcl) {
+bool GlobalRA::evenAlignNeeded(G4_Declare *dcl) {
   if (GlobalRA::useGenericAugAlign(builder.getPlatformGeneration())) {
-    // Return 0 if no special alignment is needed
-    // Return 2 if even alignment is needed
-    // Return 4 if quad alignment is needed
-
+    // Return true if even alignment is needed
     // Even align needed if for given SIMD size and elem type,
     // a complete def uses between 1-2 GRFs.
     auto kernelSimdSizeToUse = kernel.getSimdSizeWithSlicing();
@@ -2673,41 +2670,14 @@ int GlobalRA::getAlignFromAugBucket(G4_Declare *dcl) {
                topdclAugMask == AugmentationMasks::Default64Bit)
         elemSizeToUse = 8;
 
-      auto totalByteSize = elemSizeToUse * kernelSimdSizeToUse;
-      auto bucketSpans2GRFs = [&]() {
-        return totalByteSize > (unsigned)kernel.numEltPerGRF<Type_UB>() &&
-               totalByteSize <= (unsigned)(2 * kernel.numEltPerGRF<Type_UB>());
-      };
-
-      if (!(!builder.canReadR0() && dcl == kernel.fg.builder->getBuiltinR0())) {
-        if (use4GRFAlign) {
-          // The only time it's safe to do 2GRF align is when augmentation
-          // bucket is known to be Default32Bit, otherwise we need to align
-          // 4GRF. It isn't enough to simply check elemSize * GRF size to
-          // decide alignment.
-          if (topdclAugMask == AugmentationMasks::Default32Bit) {
-            if (bucketSpans2GRFs())
-              return 2;
-          } else if (topdclAugMask == AugmentationMasks::Default64Bit) {
-            if (bucketSpans2GRFs())
-              // :df SIMD16
-              return 2;
-
-            // :df SIMD32
-            return 4;
-          } else {
-            // Local RA will take this path as augmentation buckets are set
-            // to Undetermined. Although this is conservative, hybrid RA
-            // will run augmentation and compute buckets to fill in "holes".
-            // For eg, mov (32|M0) V10<2>:f should use 4GRF alignment as
-            // it's Default64Bit variable, although elem size is :f.
-            return 4;
-          }
-        } else {
-          // Even align if size is between 1-2 GRFs, for >2GRF sizes.
-          if (bucketSpans2GRFs())
-            return 2;
-        }
+      if ( // Even align if size is between 1-2 GRFs, for >2GRF sizes use weak
+           // edges
+          (elemSizeToUse * kernelSimdSizeToUse) >
+              (unsigned)kernel.numEltPerGRF<Type_UB>() &&
+          (elemSizeToUse * kernelSimdSizeToUse) <=
+              (unsigned)(2 * kernel.numEltPerGRF<Type_UB>()) &&
+          !(!builder.canReadR0() && dcl == kernel.fg.builder->getBuiltinR0())) {
+        return true;
       }
     }
   } else {
@@ -2723,28 +2693,21 @@ int GlobalRA::getAlignFromAugBucket(G4_Declare *dcl) {
             topdcl->getByteSize() >= kernel.numEltPerGRF<Type_UB>() &&
             !(!builder.canReadR0() &&
               dcl == kernel.fg.builder->getBuiltinR0())) {
-          return 2;
+          return true;
         }
       }
     }
   }
 
-  return 0;
+  return false;
 }
 
-void GlobalRA::augAlign() {
-  // Update alignment of all GRF declares based on
-  // augmentation bucket and platform.
+// This function can be invoked before local RA or after augmentation.
+void GlobalRA::evenAlign() {
+  // Update alignment of all GRF declares to align
   for (auto dcl : kernel.Declares) {
     if (dcl->getRegFile() & G4_GRF) {
-      unsigned int align = getAlignFromAugBucket(dcl);
-      if (align == 4) {
-        if (!isQuadAligned(dcl)) {
-          incRA.evenAlignUpdate(dcl);
-        }
-        forceQuadAlign(dcl);
-      }
-      else if (align == 2) {
+      if (evenAlignNeeded(dcl)) {
         if (!isEvenAligned(dcl)) {
           incRA.evenAlignUpdate(dcl);
         }
@@ -3508,8 +3471,8 @@ bool Augmentation::markNonDefaultMaskDef() {
 
     bool checkLRAAlign = false;
     if (liveAnalysis.livenessClass(G4_GRF)) {
-      if (GlobalRA::useGenericAugAlign(kernel.getPlatformGeneration()) &&
-          gra.getAlignFromAugBucket(dcl) > 0)
+      if ((GlobalRA::useGenericAugAlign(kernel.getPlatformGeneration()) &&
+           gra.evenAlignNeeded(dcl)))
         checkLRAAlign = true;
       else if (gra.getAugmentationMask(dcl) ==
                    AugmentationMasks::Default32Bit &&
@@ -3522,16 +3485,10 @@ bool Augmentation::markNonDefaultMaskDef() {
       if (dclLR) {
         int s;
         auto phyReg = dclLR->getPhyReg(s);
-        unsigned int maxAlign = 2;
-        if (gra.use4GRFAlign && gra.getAugmentationMask(dcl) == AugmentationMasks::Default64Bit) {
-          maxAlign = 4;
-        }
-        if (phyReg && phyReg->asGreg()->getRegNum() % maxAlign != 0) {
-          // If LRA assignment is not aligned as expected then
+        if (phyReg && phyReg->asGreg()->getRegNum() % 2 != 0) {
+          // If LRA assignment is not 2GRF aligned for then
           // mark it as non-default. GRA candidates cannot fully
           // overlap with such ranges. Partial overlap is illegal.
-          vISA_ASSERT(!gra.use4GRFAlign,
-                      "expecting LRA allocation to be 4GRF aligned");
           gra.setAugmentationMask(dcl, AugmentationMasks::NonDefault);
           nonDefaultMaskDefFound = true;
         }
@@ -4238,8 +4195,6 @@ bool Interference::isStrongEdgeBetween(const G4_Declare *dcl1,
 
 bool Augmentation::weakEdgeNeeded(AugmentationMasks defaultDclMask,
                                   AugmentationMasks newDclMask) {
-  if (gra.use4GRFAlign)
-    return false;
   if (useGenericAugAlign) {
     // Weak edge needed in case #GRF exceeds 2
     if (newDclMask == AugmentationMasks::Default64Bit)
@@ -4791,9 +4746,9 @@ void Augmentation::augmentIntfGraph() {
         // to 2GRF except for NoMask variables
         VISA_DEBUG_VERBOSE(std::cout
                            << "Kernel size is SIMD" << kernel.getSimdSize()
-                           << " so updating all GRFs to aug align"
+                           << " so updating all GRFs to be 2GRF aligned"
                            << "\n");
-        gra.augAlign();
+        gra.evenAlign();
       }
       gra.updateSubRegAlignment(kernel.getGRFAlign());
     }
@@ -5099,7 +5054,6 @@ void GraphColor::computeDegreeForGRF() {
       // consider weak edges in degree computation
       auto *weakEdges = intf.getCompatibleSparseIntf(lrs[i]->getDcl());
       if (weakEdges) {
-        vISA_ASSERT(!gra.use4GRFAlign, "not expecting weak edges");
         for (auto weakNeighbor : *weakEdges) {
           if (!weakNeighbor->getRegVar()->isRegAllocPartaker())
             continue;
@@ -5413,22 +5367,16 @@ void GraphColor::relaxNeighborDegreeGRF(LiveRange *lr) {
   if (!(lr->getIsPseudoNode()) && !(lr->getIsPartialDcl())) {
     unsigned lr_id = lr->getVar()->getId();
     bool lr2EvenAlign = gra.isEvenAligned(lr->getDcl());
-    unsigned int lr2AugAlign = gra.getAugAlign(lr->getDcl());
     unsigned lr2_nreg = lr->getNumRegNeeded();
 
     // relax degree between 2 nodes
     auto relaxDegree = [&](LiveRange *lr1) {
       if (lr1->getActive() && !lr1->getIsPseudoNode() &&
           !(lr1->getIsPartialDcl())) {
+        bool lr1EvenAlign = gra.isEvenAligned(lr1->getDcl());
         unsigned lr1_nreg = lr1->getNumRegNeeded();
-        unsigned w = 0;
-        if (gra.use4GRFAlign) {
-          unsigned int lr1AugAlign = gra.getAugAlign(lr1->getDcl());
-          w = edgeWeightWith4GRF(lr1AugAlign, lr2AugAlign, lr1_nreg, lr2_nreg);
-        } else {
-          bool lr1EvenAlign = gra.isEvenAligned(lr1->getDcl());
-          w = edgeWeightGRF(lr1EvenAlign, lr2EvenAlign, lr1_nreg, lr2_nreg);
-        }
+        unsigned w =
+            edgeWeightGRF(lr1EvenAlign, lr2EvenAlign, lr1_nreg, lr2_nreg);
         VISA_DEBUG_VERBOSE({
           std::cout << "\t relax ";
           lr1->dump();
@@ -5834,15 +5782,9 @@ bool GraphColor::assignColors(ColorHeuristic colorHeuristicGRF,
       if (!failed_alloc) {
         // When evenAlignNeeded is true, it is binding for correctness
         bool evenAlignNeeded = gra.isEvenAligned(lrVar->getDeclare());
-        bool quadAlignNeeded = gra.isQuadAligned(lrVar->getDeclare());
-        BankAlign align = BankAlign::Either;
-        if (quadAlignNeeded)
-          align = BankAlign::QuadGRF;
-        else if (evenAlignNeeded)
-          align = BankAlign::Even;
-
+        BankAlign align = evenAlignNeeded ? BankAlign::Even : BankAlign::Either;
         if (allocFromBanks) {
-          vISA_ASSERT(align != BankAlign::QuadGRF, "unexpected value");
+
           if (!isHybrid && oneGRFBankDivision &&
               (!evenAlignNeeded ||
                builder.getPlatformGeneration() == PlatformGen::GEN9)) {
@@ -10934,20 +10876,12 @@ void GlobalRA::insertRestoreAddr(G4_BB *bb) {
 // correctness.
 //
 unsigned GraphColor::edgeWeightGRF(const LiveRange *lr1, const LiveRange *lr2) {
+  bool lr1EvenAlign = gra.isEvenAligned(lr1->getDcl());
+  bool lr2EvenAlign = gra.isEvenAligned(lr2->getDcl());
   unsigned lr1_nreg = lr1->getNumRegNeeded();
   unsigned lr2_nreg = lr2->getNumRegNeeded();
 
-  if (gra.use4GRFAlign) {
-    auto lr1Align = gra.getAugAlign(lr1->getDcl());
-    auto lr2Align = gra.getAugAlign(lr2->getDcl());
-
-    return edgeWeightWith4GRF(lr1Align, lr2Align, lr1_nreg, lr2_nreg);
-  } else {
-    bool lr1EvenAlign = gra.isEvenAligned(lr1->getDcl());
-    bool lr2EvenAlign = gra.isEvenAligned(lr2->getDcl());
-
-    return edgeWeightGRF(lr1EvenAlign, lr2EvenAlign, lr1_nreg, lr2_nreg);
-  }
+  return edgeWeightGRF(lr1EvenAlign, lr2EvenAlign, lr1_nreg, lr2_nreg);
 }
 
 unsigned GraphColor::edgeWeightARF(const LiveRange *lr1, const LiveRange *lr2) {

visa/GraphColor.h

@@ -778,8 +778,6 @@ class Interference {
     return nullptr;
   }
 
-  size_t numVarsWithWeakEdges() const { return compatibleSparseIntf.size(); }
-
   void init() {
     if (useDenseMatrix()) {
       auto N = (size_t)rowSize * (size_t)maxId;
@@ -897,46 +895,15 @@ class GraphColor {
       return lr1_nreg + lr2_nreg - 1;
     }
 
-    unsigned sum = lr1_nreg + lr2_nreg;
-    if (!lr2EvenAlign)
+    if (!lr2EvenAlign) {
+      unsigned sum = lr1_nreg + lr2_nreg;
       return sum + 1 - ((sum) % 2);
-
-    return sum - 1 + (lr1_nreg % 2) + (lr2_nreg % 2);
-  }
-
-  static unsigned edgeWeightWith4GRF(int lr1Align, int lr2Align,
-                                     unsigned lr1_nreg, unsigned lr2_nreg) {
-    if (lr1Align < 4 && lr2Align < 4)
-      return edgeWeightGRF(lr1Align % 2, lr2Align % 2, lr1_nreg, lr2_nreg);
-
-    if (lr2Align == 4) {
-      if (lr1Align < 2)
-        return lr1_nreg + lr2_nreg - 1;
-      if (lr1Align == 2) {
-        // if (lr2_nreg % 2 == 0) -- lr2 size is even
-        // return lr2_nreg + lr1_nreg;
-        // if (lr2_nreg % 2 == 1) -- lr2 size is odd
-        // return lr2_nreg + lr1_nreg + 1;
-
-        return lr1_nreg + lr2_nreg + (lr2_nreg % 2);
-      } else if (lr1Align == 4) {
-        if (lr2_nreg % 4 == 0)
-          // lr2 size is multiple of 4
-          return lr1_nreg + lr2_nreg;
-
-        // if lr2_nreg % 4 == 1 --  lr2 size is 1 + (4*n)
-        // return lr1_nreg + lr2_nreg + 3;
-        // if lr2_nreg % 2 == 0 -- lr2 size is 2 + (4*n)
-        // return lr2_nreg + lr1_nreg + 2;
-        // if lr2_nreg % 4 == 3 -- lr2 size is 3 + (4*n)
-        // return lr2_nreg + lr1_nreg + 1;
-
-        return lr1_nreg + lr2_nreg + 4 - (lr2_nreg % 4);
-      }
+    } else if (lr2EvenAlign) {
+      return lr1_nreg + lr2_nreg - 1 + (lr1_nreg % 2) + (lr2_nreg % 2);
+    } else {
+      vISA_ASSERT_UNREACHABLE("should be unreachable");
+      return 0;
     }
-
-    vISA_ASSERT(lr1Align == 4, "unexpected condition");
-    return edgeWeightWith4GRF(lr2Align, lr1Align, lr2_nreg, lr1_nreg);
   }
 
   void computeDegreeForGRF();
@@ -1018,7 +985,7 @@ struct RAVarInfo {
   unsigned subOff = 0;
   std::vector<BundleConflict> bundleConflicts;
   G4_SubReg_Align subAlign = G4_SubReg_Align::Any;
-  int augAlignInGRF = 0;
+  bool isEvenAlign = false;
   AugmentationMasks augMask = AugmentationMasks::Undetermined;
 };
 
@@ -1143,8 +1110,6 @@ class GlobalRA {
   // The pre assigned forbidden register bits for different kinds
   ForbiddenRegs fbdRegs;
 
-  const bool use4GRFAlign = false;
-
 private:
   template <class REGION_TYPE>
   static unsigned getRegionDisp(REGION_TYPE *region, const IR_Builder &irb);
@@ -1607,35 +1572,12 @@ class GlobalRA {
     return true;
   }
 
-  bool isQuadAligned(const G4_Declare *dcl) const {
-    auto augAlign = getAugAlign(dcl);
-    return augAlign == 4;
-  }
-
-  bool isEvenAligned(const G4_Declare* dcl) const {
-    auto augAlign = getAugAlign(dcl);
-    return augAlign > 0 && augAlign % 2 == 0;
-  }
-
-  int getAugAlign(const G4_Declare *dcl) const {
-    return getVar(dcl).augAlignInGRF;
-  }
-
-  void forceQuadAlign(const G4_Declare *dcl) { setAugAlign(dcl, 4); }
-
-  void resetAlign(const G4_Declare *dcl) { setAugAlign(dcl, 0); }
-
-  // Due to legacy usage, this method takes a boolean that, when set,
-  // causes alignment to be set to Even (2). When boolean flag is
-  // reset, it also resets alignment to Either (0).
-  void setEvenAligned(const G4_Declare *dcl, bool align) {
-    setAugAlign(dcl, align ? 2 : 0);
+  bool isEvenAligned(const G4_Declare *dcl) const {
+    return getVar(dcl).isEvenAlign;
   }
 
-  void setAugAlign(const G4_Declare *dcl, int align) {
-    vISA_ASSERT(align <= 2 || use4GRFAlign, "unexpected alignment");
-    vISA_ASSERT(align <= 4, "unsupported alignment");
-    allocVar(dcl).augAlignInGRF = align;
+  void setEvenAligned(const G4_Declare *dcl, bool e) {
+    allocVar(dcl).isEvenAlign = e;
   }
 
   BankAlign getBankAlign(const G4_Declare *) const;
@@ -1650,8 +1592,7 @@ class GlobalRA {
         useLscForNonStackCallSpillFill(
             k.fg.builder->useLscForNonStackSpillFill()),
         useLscForScatterSpill(k.fg.builder->supportsLSC() &&
-                              k.fg.builder->getOption(vISA_scatterSpill)),
-        use4GRFAlign(k.fg.builder->supports4GRFAlign()) {
+                              k.fg.builder->getOption(vISA_scatterSpill)) {
     vars.resize(k.Declares.size());
 
     if (kernel.getOptions()->getOption(vISA_VerifyAugmentation)) {
@@ -1675,9 +1616,8 @@ class GlobalRA {
   static uint32_t getRefCount(int loopNestLevel);
   void updateSubRegAlignment(G4_SubReg_Align subAlign);
   bool isChannelSliced();
-  // Used by LRA/GRA/hybrid RA
-  void augAlign();
-  int getAlignFromAugBucket(G4_Declare *);
+  void evenAlign();
+  bool evenAlignNeeded(G4_Declare *);
   void getBankAlignment(LiveRange *lr, BankAlign &align);
   void printLiveIntervals();
   void reportUndefinedUses(LivenessAnalysis &liveAnalysis, G4_BB *bb,
@@ -1762,7 +1702,7 @@ class GlobalRA {
   }
 
   void copyAlignment(G4_Declare *dst, G4_Declare *src) {
-    setAugAlign(dst, getAugAlign(src));
+    setEvenAligned(dst, isEvenAligned(src));
     setSubRegAlign(dst, getSubRegAlign(src));
   }
 

visa/HWCaps.inc

@@ -846,9 +846,4 @@ bool hasReadSuppressionOrSharedLocalMemoryWAs() const {
 bool supportNativeSIMD32() const {
   return false;
 }
-
-bool supports4GRFAlign() const {
-  return false;
-}
-
 // end HW capabilities