vISA: set FFID to sr0 if there is cr0 write in the shader

DianaChen · sys_zuul · commit ccd903bfa8ea · 2019-09-22T15:07:00.000-07:00
Change-Id: I965b25ba3434c557d50b7c447bf7aea713c588ed
diff --git a/visa/BinaryEncodingIGA.cpp b/visa/BinaryEncodingIGA.cpp
@@ -610,13 +610,14 @@ void BinaryEncodingIGA::DoAll()
         return false;
     };
 
-    // Make the size of the first BB is multiple of 4 instructions, and do not compact
+    // Make the size of the first BB be multiple of 4 instructions, and do not compact
     // any instructions in it, so that the size of the first BB is multiple of 64 bytes
-    if (kernel.fg.builder->getHasPerThreadProlog())
+    if (kernel.fg.builder->getHasPerThreadProlog() ||
+        kernel.fg.builder->getHasComputeFFIDProlog())
     {
         G4_BB* first_bb = *kernel.fg.begin();
         size_t num_inst = first_bb->getInstList().size();
-        assert(num_inst != 0 && "ThreadProlog must not be empty");
+        assert(num_inst != 0 && "the first BB must not be empty");
         // label instructions don't count. Only the first instruction could be a label
         if (first_bb->getInstList().front()->isLabel())
             --num_inst;
@@ -1049,6 +1050,18 @@ void BinaryEncodingIGA::DoAll()
         assert(iter != secondBB->end() && "execpt at least one non-label inst in second BB");
         kernel.fg.builder->getJitInfo()->offsetToSkipPerThreadDataLoad = (uint32_t)(*iter)->getGenOffset();
     }
+    if (kernel.fg.builder->getHasComputeFFIDProlog())
+    {
+        // something weird will happen if both HasPerThreadProlog and HasComputeFFIDProlog
+        assert(!kernel.fg.builder->getHasPerThreadProlog());
+
+        // set offsetToSkipSetFFIDGP to the second entry's offset
+        // the first instruction in the second BB is the start of the sencond entry
+        assert(kernel.fg.getNumBB() > 1 && "expect at least one prolog BB");
+        auto secondBB = *(std::next(kernel.fg.begin()));
+        assert(!secondBB->empty() && !secondBB->front()->isLabel());
+        kernel.fg.builder->getJitInfo()->offsetToSkipSetFFIDGP = (uint32_t)secondBB->front()->getGenOffset();
+    }
 }
 
 SWSB_ENCODE_MODE BinaryEncodingIGA::getIGASWSBEncodeMode(const IR_Builder& builder) {
diff --git a/visa/BuildIR.h b/visa/BuildIR.h
@@ -511,6 +511,8 @@ class IR_Builder {
 
     int perThreadInputSize = 0;
     bool hasPerThreadProlog = false;
+    // Have inserted two entires prolog for setting FFID for compute shaders
+    bool hasComputeFFIDProlog = false;
 
 public:
     PreDefinedVars preDefVars;
@@ -616,6 +618,9 @@ class IR_Builder {
     bool getHasPerThreadProlog() const { return hasPerThreadProlog; }
     void setHasPerThreadProlog() { hasPerThreadProlog = true; }
 
+    bool getHasComputeFFIDProlog() const { return hasComputeFFIDProlog; }
+    void setHasComputeFFIDProlog() { hasComputeFFIDProlog = true; }
+
     bool isOpndAligned( G4_Operand *opnd, unsigned short &offset, int align_byte );
 
     // check if opnd is or can be made "alignByte"-byte aligned. This function will change the underlying
@@ -1099,7 +1104,7 @@ class IR_Builder {
         return inst;
     }
 
-    G4_INST* createSpill(G4_DstRegRegion* dst, G4_SrcRegRegion* header, G4_SrcRegRegion* payload, unsigned int execSize, 
+    G4_INST* createSpill(G4_DstRegRegion* dst, G4_SrcRegRegion* header, G4_SrcRegRegion* payload, unsigned int execSize,
         uint16_t numRows, uint32_t offset, G4_Declare* fp, G4_InstOption option, unsigned int lineno = 0, int CISAoff = -1,
         const char* srcFilename = nullptr)
     {
@@ -1119,7 +1124,7 @@ class IR_Builder {
         auto builtInR0 = getBuiltinR0();
         auto rd = getRegionStride1();
         auto srcRgnr0 = createSrcRegRegion(Mod_src_undef, Direct, builtInR0->getRegVar(), 0, 0, rd, Type_UD);
-        G4_INST* spill = createIntrinsicInst(nullptr, Intrinsic::Spill, execSize, dst, 
+        G4_INST* spill = createIntrinsicInst(nullptr, Intrinsic::Spill, execSize, dst,
             srcRgnr0, payload, nullptr, option, lineno);
         spill->asSpillIntrinsic()->setSrcFilename(srcFilename);
         spill->asSpillIntrinsic()->setCISAOff(CISAoff);
@@ -1129,7 +1134,7 @@ class IR_Builder {
         return spill;
     }
 
-    G4_INST* createFill(G4_SrcRegRegion* header, G4_DstRegRegion* dstData, unsigned int execSize, uint16_t numRows, uint32_t offset, 
+    G4_INST* createFill(G4_SrcRegRegion* header, G4_DstRegRegion* dstData, unsigned int execSize, uint16_t numRows, uint32_t offset,
         G4_Declare* fp, G4_InstOption option, unsigned int lineno = 0, int CISAoff = -1, const char* srcFilename = nullptr)
     {
         G4_INST* fill = createIntrinsicInst(nullptr, Intrinsic::Fill, execSize, dstData,
diff --git a/visa/Optimizer.cpp b/visa/Optimizer.cpp
@@ -596,6 +596,7 @@ void Optimizer::initOptimizations()
     INITIALIZE_PASS(dce,                     vISA_EnableDCE,               TIMER_OPTIMIZER);
     INITIALIZE_PASS(reassociateConst,        vISA_reassociate,             TIMER_OPTIMIZER);
     INITIALIZE_PASS(split4GRFVars,           vISA_split4GRFVar,            TIMER_OPTIMIZER);
+    INITIALIZE_PASS(addFFIDProlog,           vISA_addFFIDProlog,           TIMER_MISC_OPTS);
     INITIALIZE_PASS(loadThreadPayload,       vISA_loadThreadPayload,       TIMER_MISC_OPTS);
     INITIALIZE_PASS(insertFenceBeforeEOT,    vISA_EnableAlways,            TIMER_MISC_OPTS);
     INITIALIZE_PASS(insertScratchReadBeforeEOT, vISA_clearScratchWritesBeforeEOT, TIMER_MISC_OPTS);
@@ -1191,6 +1192,8 @@ int Optimizer::optimization()
 
     runPass(PI_loadThreadPayload);
 
+    runPass(PI_addFFIDProlog);
+
     // Insert a dummy compact instruction if requested for SKL+
     runPass(PI_insertDummyCompactInst);
 
@@ -8067,6 +8070,137 @@ void genBucket(G4_INST *send, Bucket *bucket, RW rwType) {
         }
     }
 
+    // create prolog to set sr0 to FFID. TGL WA.
+    // Do only when there is cr0 write inside the kernel
+    void Optimizer::addFFIDProlog()
+    {
+        if (!builder.getIsKernel())
+            return;
+
+        FFID ffid = static_cast<FFID>(builder.getOptions()->getuInt32Option(vISA_setFFID));
+        // return if FFID is not given
+        if (ffid == FFID_INVALID)
+            return;
+
+        // return if there is no cr0 write
+        bool has_cr0_dst = false;
+        for (auto bb : kernel.fg)
+        {
+            for (G4_INST* inst : *bb)
+            {
+                if (inst->getDst() != nullptr &&
+                    inst->getDst()->asDstRegRegion()->getBase()->isCrReg())
+                {
+                    has_cr0_dst = true;
+                    break;
+                }
+            }
+            if (has_cr0_dst)
+                break;
+        }
+        if (!has_cr0_dst)
+            return;
+
+        // get r127.0 decl
+        G4_Declare* rtail =
+            builder.createHardwiredDeclare(8, Type_UD, kernel.getNumRegTotal() - 1, 0);
+
+        // (W) and (1|M0)  r127.0 <1>:ud   sr0.0 <0;1,0>:ud  0xF0FFFFFF:ud
+        auto createAnd = [this, &rtail]()
+        {
+            auto src0 = builder.createSrcRegRegion(
+                Mod_src_undef, Direct, builder.phyregpool.getSr0Reg(), 0, 0,
+                builder.getRegionScalar(), Type_UD);
+            auto src1 = builder.createImm(0xF0FFFFFF, Type_UD);
+            auto dst = builder.createDstRegRegion(Direct, rtail->getRegVar(), 0, 0, 1, Type_UD);
+
+            return builder.createInternalInst(nullptr, G4_and, nullptr, false, 1,
+                dst, src0, src1, InstOpt_WriteEnable);
+        };
+
+        // (W) or  (1|M0)  sr0.0<1>:ud   127.0<0;1,0>:ud    imm:ud
+        auto createOr = [this, &rtail](uint32_t imm)
+        {
+            auto src0 = builder.createSrcRegRegion(
+                Mod_src_undef, Direct, rtail->getRegVar(), 0, 0,
+                builder.getRegionScalar(), Type_UD);
+            auto src1 = builder.createImm(imm, Type_UD);
+            auto dst = builder.createDstRegRegion(Direct,
+                builder.phyregpool.getSr0Reg(), 0, 0, 1, Type_UD);
+
+            return builder.createInternalInst(nullptr, G4_or, nullptr, false, 1,
+                dst, src0, src1, InstOpt_WriteEnable);
+        };
+
+        // (W) jmpi (1|M0) label
+        auto createJmpi = [this](G4_Label* label)
+        {
+            return builder.createInternalInst(nullptr, G4_jmpi, nullptr, false, 1,
+                nullptr, label, nullptr, InstOpt_WriteEnable);
+        };
+
+        auto createLabelInst = [this](G4_Label* label)
+        {
+            return kernel.fg.createNewLabelInst(label);
+        };
+
+        // for compute shader, create two entris
+        if (ffid == FFID_GP || ffid == FFID_GP1)
+        {
+            // Entry0: Set sr0 to FFID_GP (0x7)
+            //     (W) and (1|M0)  r127.0 <1>:ud   sr0.0 <0;1,0>:ud   0xF0FFFFFF:ud
+            //     (W) or  (1|M0)  sr0.0<1>:ud     127.0<0;1,0>:ud    0x07000000:ud
+            //     jmpi ffid_prolog_end
+            // Entry1: Set sr0 to FFID_GP1 (0x8)
+            //     (W) and (1|M0)  r127.0 <1>:ud   sr0.0 <0;1,0>:ud   0xF0FFFFFF:ud
+            //     (W) or  (1|M0)  sr0.0<1>:ud     127.0<0;1,0>:ud    0x08000000:ud
+            //     ffid_prolog_end:
+
+            // Put the entry0 block into a new BB, so that we can make it 64-bit
+            // aligned in BinaryEncodingIGA
+            G4_BB* entry_0_bb = kernel.fg.createNewBB();
+            entry_0_bb->push_back(createAnd());
+            entry_0_bb->push_back(createOr(0x07000000));
+
+            // get jmp target label. If the next bb has no label, create one and insert it
+            // at the beginning
+            G4_Label* jmp_label = nullptr;
+            assert(kernel.fg.begin() != kernel.fg.end());
+            G4_BB* next_bb = *kernel.fg.begin();
+            if (next_bb->front()->isLabel())
+            {
+                jmp_label = next_bb->front()->getSrc(0)->asLabel();
+            }
+            else
+            {
+                std::string label_name("ffid_prolog_end");
+                jmp_label = builder.createLabel(label_name, LABEL_BLOCK);
+                next_bb->insert(next_bb->begin(), createLabelInst(jmp_label));
+            }
+            entry_0_bb->push_back(createJmpi(jmp_label));
+
+            // Put the rest in another BB
+            G4_BB* entry_1_bb = kernel.fg.createNewBB();
+            entry_1_bb->push_back(createAnd());
+            entry_1_bb->push_back(createOr(0x08000000));
+
+            // add these two BB to be the first two in the shader
+            kernel.fg.addPrologBB(entry_1_bb);
+            kernel.fg.addPrologBB(entry_0_bb);
+            builder.setHasComputeFFIDProlog();
+        }
+        else
+        {
+            // for other shaders, set the FFID
+            //     (W) and (1|M0)  r127.0 <1>:ud   sr0.0 <0;1,0>:ud   0xF0FFFFFF:ud
+            //     (W) or  (1|M0)  sr0.0<1>:ud     127.0<0;1,0>:ud    (FFID << 24):ud
+            G4_BB* bb = kernel.fg.createNewBB();
+            bb->push_back(createAnd());
+            bb->push_back(createOr(ffid << 24));
+            kernel.fg.addPrologBB(bb);
+        }
+    }
+
     void Optimizer::loadThreadPayload()
     {
     }
diff --git a/visa/Optimizer.h b/visa/Optimizer.h
@@ -244,6 +244,7 @@ class Optimizer
     void clearARFDependencies();
     void clearSendDependencies();
     void loadThreadPayload();
+    void addFFIDProlog();
     void insertFenceBeforeEOT();
     void insertScratchReadBeforeEOT();
     void resetA0();
@@ -337,6 +338,7 @@ class Optimizer
         PI_reassociateConst,
         PI_split4GRFVars,
         PI_loadThreadPayload,
+        PI_addFFIDProlog,
         PI_insertFenceBeforeEOT,
         PI_insertScratchReadBeforeEOT,
         PI_mapOrphans,
diff --git a/visa/include/JitterDataStruct.h b/visa/include/JitterDataStruct.h
@@ -75,7 +75,12 @@ typedef struct _CM_JIT_INFO {
     unsigned int freeGRFInfoSize;
     unsigned char numBytesScratchGtpin;
 
-    uint32_t offsetToSkipPerThreadDataLoad = 0; 
+    uint32_t offsetToSkipPerThreadDataLoad = 0;
+
+    // When two entries prolog is added for setting FFID
+    // for compute (GP or GP1), skip this offset to set FFID_GP1.
+    // Will set FFID_GP if not skip
+    uint32_t offsetToSkipSetFFIDGP = 0;
 } FINALIZER_INFO;
 
 #endif // _CM_JITTERDATASTRUCT_
diff --git a/visa/include/VISAOptions.def b/visa/include/VISAOptions.def
@@ -208,6 +208,8 @@ DEF_VISA_OPTION(vISA_GetFreeGRFInfo,      ET_BOOL,  "-getfreegrfinfo",    UNUSED
 DEF_VISA_OPTION(vISA_clearScratchWritesBeforeEOT,   ET_BOOL,  NULLSTR, UNUSED, false)
 DEF_VISA_OPTION(vISA_clearHDCWritesBeforeEOT,       ET_BOOL,  NULLSTR, UNUSED, false)
 DEF_VISA_OPTION(vISA_setA0toTdrForSendc,            ET_BOOL,  "-setA0toTdrForSendc", UNUSED, false)
+DEF_VISA_OPTION(vISA_addFFIDProlog,                 ET_BOOL,  "-noFFIDProlog",       UNUSED, true)
+DEF_VISA_OPTION(vISA_setFFID,                       ET_INT32, "-setFFID", "USAGE: -setFFID <ffid>\n", FFID_INVALID)
 
 //=== HW debugging options ===
 DEF_VISA_OPTION(vISA_GenerateDebugInfo,   ET_BOOL,  "-generateDebugInfo", UNUSED, false)
diff --git a/visa/include/visa_igc_common_header.h b/visa/include/visa_igc_common_header.h
@@ -625,4 +625,21 @@ typedef struct _vISA_RT_CONTROLS
 } vISA_RT_CONTROLS;
 
 
+// FixedFunctionID: these are hardware FFID values
+enum FFID
+{
+    FFID_NULL = 0x0,
+    FFID_VSR  = 0x3,
+    FFID_HS   = 0x4,
+    FFID_DS   = 0x5,
+    FFID_TS   = 0x6,
+    FFID_GP   = 0x7,
+    FFID_GP1  = 0x8,
+    FFID_VS   = 0x9,
+    FFID_GS   = 0xC,
+    FFID_PS   = 0xF,
+
+    FFID_INVALID = 0xFF
+};
+
 #endif
