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DianaChenZuul
DianaChen
authored and
Zuul
committed
IGA: Clean-up code to sppress compiler warnings
Change-Id: I8634e66a7ace8d90ce537d79c46980fb38663ea4
1 parent 6a557e0 commit cda06a3

25 files changed

+174
-162
lines changed

‎visa/BinaryEncodingIGA.cpp

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -845,7 +845,6 @@ void BinaryEncodingIGA::DoAll()
845845
SendDescArg BinaryEncodingIGA::getIGASendDescArg(G4_INST* sendInst) const
846846
{
847847
SendDescArg desc;
848-
desc.init();
849848
assert(sendInst->isSend() && "expect send inst");
850849
G4_Operand* msgDesc = sendInst->isSplitSend() ? sendInst->getSrc(2) : sendInst->getSrc(1);
851850
if (msgDesc->isImm())
@@ -867,7 +866,7 @@ SendDescArg BinaryEncodingIGA::getIGASendDescArg(G4_INST* sendInst) const
867866

868867
iga::SendDescArg BinaryEncodingIGA::getIGASendExDescArg(G4_INST* sendInst) const
869868
{
870-
iga::SendDescArg exDescArg{ };
869+
iga::SendDescArg exDescArg;
871870

872871
assert(sendInst->isSend() && "expect send inst");
873872
if (sendInst->isSplitSend())

‎visa/iga/IGALibrary/Backend/GED/Decoder.cpp

Lines changed: 7 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -101,7 +101,8 @@ DecoderBase::DecoderBase(const Model &model, ErrorHandler &errHandler) :
101101
GEDBitProcessor(model,errHandler),
102102
m_gedModel(IGAToGEDTranslation::lowerPlatform(model.platform)),
103103
m_kernel(nullptr),
104-
m_opSpec(nullptr)
104+
m_opSpec(nullptr),
105+
m_binary(nullptr)
105106
{
106107
IGA_ASSERT(m_gedModel != GED_MODEL_INVALID, "invalid GED model");
107108
}
@@ -492,7 +493,7 @@ void DecoderBase::decodeBasicDestinationAlign16(Instruction *inst)
492493
GED_DECODE_RAW(int32_t, addrImm, DstAddrImm);
493494

494495
GED_DECODE_RAW(uint32_t, subRegNum, DstAddrSubRegNum);
495-
RegRef a0 = {0, (uint8_t)subRegNum};
496+
RegRef a0 = RegRef(0, (uint8_t)subRegNum);
496497
inst->setInidirectDestination(
497498
dstMod, a0, (uint16_t)addrImm, Region::Horz::HZ_1, type);
498499
break;
@@ -622,7 +623,7 @@ void DecoderBase::decodeTernaryDestinationAlign16(Instruction *inst)
622623
GED_DECODE_RAW(GED_DST_CHAN_EN, chEn, DstChanEn);
623624

624625
RegName regName = RegName::INVALID;
625-
RegRef regRef{0,0};
626+
RegRef regRef;
626627
decodeReg(-1, regFile, regNumBits, regName, regRef);
627628

628629
if (inst->isMacro()) {
@@ -766,7 +767,7 @@ void DecoderBase::decodeTernarySourceAlign16(Instruction *inst)
766767

767768
if (isMacro) {
768769
MathMacroExt MathMacroReg = decodeSrcMathMacroReg<S>();
769-
RegRef rr = {(uint8_t)regNum, 0};
770+
RegRef rr = RegRef((uint8_t)regNum, 0);
770771
Region macroDftSrcRgn = macroDefaultSourceRegion(
771772
(int)S, inst->getOpSpec(), m_model.platform, inst->getExecSize());
772773
inst->setMacroSource(
@@ -780,10 +781,7 @@ void DecoderBase::decodeTernarySourceAlign16(Instruction *inst)
780781
} else {
781782
int subReg = type == Type::INVALID ?
782783
0 : binNumToSubRegNum(decodeSrcSubRegNum<S>(), RegName::GRF_R, type);
783-
RegRef reg = {
784-
(uint8_t)regNum,
785-
(uint8_t)subReg
786-
};
784+
RegRef reg = RegRef((uint8_t)regNum, (uint8_t)subReg);
787785
Region rgn;
788786
if (decodeSrcRepCtrl<S>() == GED_REP_CTRL_NoRep) {
789787
GED_SWIZZLE swizzle[4];
@@ -927,7 +925,7 @@ void DecoderBase::decodeTernarySourceAlign1(Instruction *inst)
927925
if (m_model.supportsAlign16ImplicitAcc()) {
928926
fatal("src%d: macro instructions must be Align16 for this platform.", (int)S);
929927
}
930-
RegRef regRef{0,0};
928+
RegRef regRef;
931929
RegName regName = decodeSourceReg<S>(regRef);
932930
Region macroDftSrcRgn = macroDefaultSourceRegion(
933931
(int)S, inst->getOpSpec(), m_model.platform, inst->getExecSize());

‎visa/iga/IGALibrary/Backend/GED/Decoder.hpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -39,9 +39,9 @@ namespace iga
3939
RegRef reg;
4040
};
4141
struct DirRegOpInfo {
42-
RegName regName; // e.g. "r" or "acc"
42+
RegName regName = RegName::INVALID; // e.g. "r" or "acc"
4343
RegRef regRef; // 13
44-
Type type;
44+
Type type = Type::INVALID;
4545
};
4646

4747
class DecoderBase : public GEDBitProcessor

‎visa/iga/IGALibrary/Backend/GED/Encoder.hpp

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -138,7 +138,7 @@ namespace iga
138138
// state that is valid over encodeInst()
139139
ged_ins_t m_gedInst;
140140
bool m_encodeAlign16 = false;
141-
Op m_opcode;
141+
Op m_opcode = Op::INVALID;
142142
size_t m_numberInstructionsEncoded;
143143

144144
private:
@@ -214,7 +214,7 @@ namespace iga
214214
/////////////////////////////////////////////////////////////
215215
// state valid over encodeKernel()
216216
MemManager *m_mem;
217-
uint8_t *m_instBuf; // the output bits
217+
uint8_t *m_instBuf = nullptr; // the output bits
218218
struct JumpPatch { // JIP and UIP label patching
219219
Instruction *inst; // the instruction
220220
ged_ins_t gedInst; // the partially constructed GED instruction
@@ -375,7 +375,7 @@ namespace iga
375375
RegName regName,
376376
uint8_t regNum)
377377
{
378-
uint32_t regBits;
378+
uint32_t regBits = 0;
379379
if (regName == RegName::GRF_R) {
380380
regBits = regNum; // GRF fast path
381381
} else { // ARF slower path

‎visa/iga/IGALibrary/Backend/GED/GEDToIGATranslation.hpp

Lines changed: 2 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -497,7 +497,8 @@ namespace iga
497497
// TODO: remove this an retain only translate<GED_CHANNEL_OFFSET>
498498
static ChannelOffset translate(GED_EXEC_MASK_OFFSET_CTRL ctrl)
499499
{
500-
ChannelOffset mOffset;
500+
assert(ctrl != GED_EXEC_MASK_OFFSET_CTRL_INVALID);
501+
ChannelOffset mOffset = ChannelOffset::M0;
501502

502503
switch (ctrl)
503504
{
@@ -535,11 +536,9 @@ namespace iga
535536
mOffset = ChannelOffset::M0;
536537
break;
537538
}
538-
539539
return mOffset;
540540
}
541541

542-
543542
static MaskCtrl translate(GED_MASK_CTRL cntrl)
544543
{
545544
MaskCtrl mCtrl;

‎visa/iga/IGALibrary/Backend/Native/InstEncoder.hpp

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -60,8 +60,8 @@ namespace iga
6060

6161
struct InstEncoderState
6262
{
63-
int instIndex;
64-
const Instruction *inst;
63+
int instIndex = 0;
64+
const Instruction* inst = nullptr;
6565
#ifdef IGA_VALIDATE_BITS
6666
// All the bit fields set by some field during this instruction encoding
6767
// e.g. if a field with bits [127:96] is set to 00000000....0001b
@@ -493,11 +493,11 @@ namespace iga
493493

494494

495495
class InstCompactor : public BitProcessor {
496-
const OpSpec *os;
496+
const OpSpec *os = nullptr;
497497

498498
MInst compactedBits;
499499
MInst uncompactedBits;
500-
CompactionDebugInfo *compactionDebugInfo;
500+
CompactionDebugInfo *compactionDebugInfo = nullptr;
501501
bool compactionMissed = false;
502502

503503
// the compaction result (if compaction enabled)

‎visa/iga/IGALibrary/Backend/Native/MInst.hpp

Lines changed: 5 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -35,8 +35,12 @@ namespace iga
3535
{
3636
// machine instruction
3737
struct MInst {
38+
MInst() {
39+
dw0 = dw1 = dw2 = dw3 = 0;
40+
}
41+
3842
union {
39-
struct {uint32_t dw0, dw1, dw2, dw3;};
43+
struct {uint32_t dw0, dw1, dw2, dw3; };
4044
struct {uint32_t dws[4];};
4145
struct {uint64_t qw0, qw1;};
4246
struct {uint64_t qws[2];};

‎visa/iga/IGALibrary/Frontend/BufferedLexer.hpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -71,7 +71,7 @@ static void WriteTokenContext(
7171
if (loc.offset >= (PC)inp.size()) {
7272
os << "<<EOF>>" << std::endl;
7373
} else if (loc.line > 0) {
74-
size_t k = loc.offset - loc.col + 1;
74+
size_t k = static_cast<size_t>(loc.offset) - loc.col + 1;
7575
while (k < inp.size() && inp[k] != '\n' && inp[k] != '\r')
7676
os << inp[k++];
7777
os << std::endl;

‎visa/iga/IGALibrary/Frontend/Formatter.cpp

Lines changed: 5 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -68,7 +68,7 @@ class Formatter : public BasicFormatter
6868
const FormatOpts& opts;
6969
struct ColumnPreferences cols;
7070
const Instruction *currInst;
71-
const uint8_t *bits; // optional bits to render
71+
const uint8_t *bits = nullptr; // optional bits to render
7272

7373
void warning(const char *msg) {
7474
if (currInst) {
@@ -814,7 +814,7 @@ void Formatter::formatRegister(
814814
// - caller demands it (e.g. it's a nonsend) AND
815815
// the register chosen has subregisters (e.g. not ce and null)
816816
// - OR it's non-zero (either bad IR or something's there)
817-
if ((emitSubReg && ri->hasSubregs()) || reg.subRegNum != 0) {
817+
if (emitSubReg && ri->hasSubregs() || reg.subRegNum != 0) {
818818
emit('.');
819819
emit((int)reg.subRegNum);
820820
}
@@ -1292,7 +1292,7 @@ static const char* MessageTypeEnumerationDisassembly[64] =
12921292
"Scratch Block Read", // 0
12931293
"Scratch Block Write", // 1
12941294
"OWord Block Read", // 2
1295-
"Aligned OWord Block Read", // 3
1295+
"Unaligned OWord Block Read", // 3
12961296
"OWord Dual Block Read", // 4
12971297
"DWord Scattered Read", // 5
12981298
"Byte Scattered Read", // 6
@@ -1606,7 +1606,8 @@ void Formatter::EmitSendDescriptorInfoGED(
16061606
msgType = GED_GetMessageTypeDP_SAMPLER(desc, gedP, &getRetVal);
16071607
} else if (sfid == SFID_DP_RC) {
16081608
msgType = GED_GetMessageTypeDP_RC(desc, gedP, &getRetVal);
1609-
} else if (sfid == SFID_DP_CC || sfid == SFID_DP_DCRO) { // ccdp SFID_DP_CC Constant Cache Data Port
1609+
} else if (sfid == SFID_DP_CC) {
1610+
// SFID_DP_DCRO and SFID_DP_CC have the same value: Constant Cache Data Port
16101611
if (p < iga::Platform::GEN9) {
16111612
msgType = GED_GetMessageTypeDP_CC(desc, gedP, &getRetVal);
16121613
}

‎visa/iga/IGALibrary/Frontend/KernelParser.cpp

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1413,7 +1413,7 @@ class KernelParser : GenParser
14131413
}
14141414
const char *p = &m_lexer.GetSource()[tk.loc.offset];
14151415
std::string s;
1416-
s.reserve(tk.loc.extent + 1);
1416+
s.reserve((size_t)tk.loc.extent + 1);
14171417
for (size_t i = 0; i < tk.loc.extent; i++) {
14181418
s += *p++;
14191419
}
@@ -1726,6 +1726,7 @@ class KernelParser : GenParser
17261726
if (LookingAt(LBRACK)) {
17271727
ParseDstOpRegInd(opStart, regNum * 32);
17281728
} else {
1729+
assert(regInfo != nullptr);
17291730
FinishDstOpRegDirSubRegRgnTy(
17301731
opStart, regStart, *regInfo, regNum);
17311732
}
@@ -1860,7 +1861,8 @@ class KernelParser : GenParser
18601861
if (dty != Type::INVALID) {
18611862
int typeSize = TypeSizeInBits(dty)/8;
18621863
if (!ri.isSubRegByteOffsetValid(regNum, subregNum * typeSize, m_model.getGRFByteSize())) {
1863-
Warning(subregLoc, "subregister out of bounds for data type");
1864+
Error(subregLoc,
1865+
"subregister out of bounds for data type", ToSyntax(dty));
18641866
} else if (typeSize < ri.accGran) {
18651867
Warning(regnameLoc, "access granularity too small for data type");
18661868
}
@@ -2861,7 +2863,6 @@ class KernelParser : GenParser
28612863
void ParseSendDescs() {
28622864
const Loc exDescLoc = NextLoc();
28632865
SendDescArg exDesc;
2864-
exDesc.init();
28652866
if (ParseAddrRegRefOpt(exDesc.reg)) {
28662867
exDesc.type = SendDescArg::REG32A;
28672868
} else {
@@ -2884,7 +2885,6 @@ class KernelParser : GenParser
28842885

28852886
const Loc descLoc = NextLoc();
28862887
SendDescArg desc;
2887-
desc.init();
28882888
if (ParseAddrRegRefOpt(desc.reg)) {
28892889
desc.type = SendDescArg::REG32A;
28902890
} else {

‎visa/iga/IGALibrary/Frontend/LdStSyntax/MessageParsing.cpp

Lines changed: 7 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -34,9 +34,9 @@ using namespace iga;
3434

3535

3636
struct RegRange {
37-
RegName regName;
38-
int regStart;
39-
int length;
37+
RegName regName = RegName::INVALID;
38+
int regStart = 0;
39+
int length = 0;
4040
};
4141

4242
// e.g. r13
@@ -122,24 +122,24 @@ static MAddrModel parseAddressModel(GenParser &p)
122122
// AddrModel [r13,r14 + 0x100]
123123
struct AddrOperand {
124124
Loc addrModelLoc;
125-
MAddrModel addrModel;
125+
MAddrModel addrModel = INVALID_ADDR_MODEL;
126126

127127
RegRange addrReg0;
128128
Loc addrReg0Loc;
129129

130130
RegRange addrReg1;
131131
Loc addrReg1Loc;
132132

133-
int32_t addrOff;
133+
int32_t addrOff = 0;
134134
Loc addrOffLoc;
135135

136-
Type addrType;
136+
Type addrType = Type::INVALID;
137137
};
138138

139139
struct DataOperand {
140140
Loc loc;
141141
RegRange reg;
142-
Type type;
142+
Type type = Type::INVALID;
143143
};
144144

145145
struct LdStSyntax {
@@ -591,11 +591,9 @@ static void encodeDescriptors(
591591

592592
// set the descriptors!
593593
SendDescArg exDescArg;
594-
exDescArg.init();
595594
exDescArg.type = SendDescArg::IMM;
596595
exDescArg.imm = exDesc;
597596
SendDescArg descArg;
598-
descArg.init();
599597
descArg.type = SendDescArg::IMM;
600598
descArg.imm = desc;
601599
handler.InstSendDescs(

‎visa/iga/IGALibrary/Frontend/Parser.hpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -57,7 +57,7 @@ namespace iga
5757
, message(m)
5858
{
5959
}
60-
~SyntaxError() throw () { }
60+
~SyntaxError() { }
6161
};
6262

6363
///////////////////////////////////////////////////////////////////////////
@@ -278,7 +278,7 @@ namespace iga
278278
{
279279
for (size_t i = 2; i < len; i++) {
280280
char chr = src[off + i];
281-
T dig = 0;
281+
char dig = 0;
282282
if (chr >= '0' && chr <= '9')
283283
dig = chr - '0';
284284
else if (chr >= 'A' && chr <= 'F')

‎visa/iga/IGALibrary/IR/BitSet.hpp

Lines changed: 4 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -321,7 +321,10 @@ bool BitSet<I>::operator==(const BitSet<I> &bs) const
321321
// do we have to worry about the ragged padding.
322322
// e.g. given 32b words if the bitset is 31 bits long, we have to
323323
// worry about the trailing bit
324-
return memcmp(&words[0], &bs.words[0], sizeof(words)) == 0;
324+
if (N != bs.N) { // We should not compare BitSets of different size
325+
return false;
326+
}
327+
return memcmp(&words[0], &bs.words[0], wordsSize * sizeof(I)) == 0;
325328
}
326329

327330
} // namespace iga

‎visa/iga/IGALibrary/IR/ImmVal.hpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -62,9 +62,9 @@ namespace iga
6262
uint8_t u8;
6363
uint16_t u16;
6464
uint32_t u32;
65-
uint64_t u64;
65+
uint64_t u64 = 0;
6666
};
67-
Kind kind;
67+
Kind kind = Kind::UNDEF;
6868

6969
ImmVal& operator=(uint8_t x);
7070
ImmVal& operator=(int8_t x);

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