Allow small spills for PS SIMD8 and SIMD16

Change-Id: I16062b116e9c0bb680909f6c9a59e88a73fd9cbd

Author: fftzeng

IGC/Compiler/CISACodeGen/CISABuilder.cpp

@@ -3701,7 +3701,11 @@ namespace IGC
             {
                 // 2 means #spill/fill is roughly 1% of #inst
                 // ToDo: tune the threshold
-                SaveOption(vISA_AbortOnSpillThreshold, 2u);
+                if (m_program->m_dispatchSize == SIMDMode::SIMD8)
+                    SaveOption(vISA_AbortOnSpillThreshold, IGC_GET_FLAG_VALUE(SIMD8_SpillThreshold) * 2);
+
+                else if (m_program->m_dispatchSize == SIMDMode::SIMD16)
+                    SaveOption(vISA_AbortOnSpillThreshold, IGC_GET_FLAG_VALUE(SIMD16_SpillThreshold) * 2);
             }
         }
 

IGC/common/igc_flags.def

@@ -31,6 +31,8 @@ DECLARE_IGC_REGKEY(bool, EnableVISAPreSched,            true,  "Enable VISA Pre-
 DECLARE_IGC_REGKEY(DWORD, VISAPreSchedCtrl,             0,     "Configure Pre-RA Scheduler, default(0), logging(1), latency(2), pressure(4)")
 DECLARE_IGC_REGKEY(bool, ForceVISAPreSched,             false, "Force enabling of VISA Pre-RA Scheduler")
 DECLARE_IGC_REGKEY(DWORD, VISAPreSchedRPThreshold,      0,     "Configure how aggressive pre-RA Scheduler is, 0 for the default")
+DECLARE_IGC_REGKEY(DWORD, SIMD8_SpillThreshold,         2,     "Percentage of instructions allowed for spilling")
+DECLARE_IGC_REGKEY(DWORD, SIMD16_SpillThreshold,        2,     "Percentage of instructions allowed for spilling")
 DECLARE_IGC_REGKEY(bool, DisableCSEL,                   false, "disable csel peep-hole")
 DECLARE_IGC_REGKEY(bool, DisableFlagOpt,                false, "Disable optimization cmp with logic op")
 DECLARE_IGC_REGKEY(bool, DisableIfCvt,                  false, "Disable ifcvt")