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Add functional lit tests for several passes
Added tests
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‎IGC/AdaptorCommon/ProcessFuncAttributes.cpp

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -844,6 +844,8 @@ bool ProcessBuiltinMetaData::runOnModule(Module& M)
844844
}
845845
Changed = true;
846846
}
847+
if (Changed)
848+
m_pMdUtil->save(M.getContext());
847849

848850
return Changed;
849851
}

‎IGC/Compiler/tests/AdvCodeMotion/hoist-uni.ll

Lines changed: 133 additions & 0 deletions
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@@ -0,0 +1,133 @@
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;=========================== begin_copyright_notice ============================
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;
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; Copyright (C) 2022 Intel Corporation
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;
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; SPDX-License-Identifier: MIT
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;
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;============================ end_copyright_notice =============================
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;
9+
; RUN: igc_opt -debugify -adv-codemotion-cm=1 -igc-advcodemotion -check-debugify -S < %s 2>&1 | FileCheck %s
10+
; ------------------------------------------------
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; AdvCodeMotion
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; ------------------------------------------------
13+
14+
; Debug-info related check
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; CHECK-NOT: WARNING
16+
; CHECK: CheckModuleDebugify: PASS
17+
18+
define spir_kernel void @test(i32 addrspace(1)* %dst, <8 x i32> %r0, <8 x i32> %payloadHeader, i16 %localIdX, i16 %localIdY, i16 %localIdZ, <3 x i32> %globalSize, <3 x i32> %enqueuedLocalSize, <3 x i32> %localSize, i8* %privateBase, i32 %bufferOffset) #0 {
19+
20+
; CHECK-LABEL: @test(
21+
; CHECK: entry:
22+
; CHECK: [[TMP0:%[A-z0-9]*]] = extractelement <8 x i32> [[R0:%[A-z0-9]*]], i32 1
23+
; CHECK: [[TMP1:%[A-z0-9]*]] = extractelement <3 x i32> [[GLOBALSIZE:%[A-z0-9]*]], i32 0
24+
; CHECK: [[TMP2:%[A-z0-9]*]] = extractelement <3 x i32> [[LOCALSIZE:%[A-z0-9]*]], i32 0
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; CHECK: [[TMP3:%[A-z0-9]*]] = extractelement <3 x i32> [[ENQUEUEDLOCALSIZE:%[A-z0-9]*]], i32 0
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; CHECK: [[TMP4:%[A-z0-9]*]] = mul i32 [[TMP3]], [[TMP0]]
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; CHECK: [[TMP5:%[A-z0-9]*]] = zext i16 [[LOCALIDX:%[A-z0-9]*]] to i32
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; CHECK: [[TMP6:%[A-z0-9]*]] = add i32 [[TMP5]], [[TMP4]]
29+
; CHECK: [[TMP7:%[A-z0-9]*]] = extractelement <8 x i32> [[PAYLOADHEADER:%[A-z0-9]*]], i32 0
30+
; CHECK: [[TMP8:%[A-z0-9]*]] = add i32 [[TMP6]], [[TMP7]]
31+
; CHECK: br label [[BB3:%[A-z0-9]*]]
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; CHECK: bb1:
33+
; CHECK: [[A:%[A-z0-9]*]] = phi i32 [ [[B:%[A-z0-9]*]], [[BB3]] ], [ [[AI:%[A-z0-9]*]], [[BB1:%[A-z0-9]*]] ]
34+
; CHECK: [[LC:%[A-z0-9]*]] = phi i32 [ [[BI:%[A-z0-9]*]], [[BB3]] ], [ [[LC]], [[BB1]] ]
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; CHECK: [[AI]] = add i32 [[A]], 1
36+
; CHECK: [[AC:%[A-z0-9]*]] = icmp ne i32 [[TMP8]], [[AI]]
37+
; CHECK: [[CC:%[A-z0-9]*]] = icmp eq i32 [[AI]], [[LC]]
38+
; CHECK: br i1 [[CC]], label [[BB2:%[A-z0-9]*]], label [[BB1]]
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; CHECK: bb2:
40+
; CHECK: [[AAA:%[A-z0-9]*]] = add i32 [[TMP1]], [[TMP2]]
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; CHECK: br i1 [[AC]], label [[TBB:%[A-z0-9]*]], label [[FBB:%[A-z0-9]*]]
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; CHECK: bb3:
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; CHECK: [[B]] = phi i32 [ -1, [[ENTRY:%[A-z0-9]*]] ], [ [[BI]], [[JOIN:%[A-z0-9]*]] ]
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; CHECK: [[BL:%[A-z0-9]*]] = phi i32 [ 0, [[ENTRY]] ], [ [[BLI:%[A-z0-9]*]], [[JOIN]] ]
45+
; CHECK: [[BI]] = add i32 [[B]], [[TMP2]]
46+
; CHECK: [[BLI]] = add i32 [[BL]], [[TMP2]]
47+
; CHECK: [[BC:%[A-z0-9]*]] = icmp ult i32 [[BLI]], [[TMP1]]
48+
; CHECK: br i1 [[BC]], label [[BB1]], label [[END:%[A-z0-9]*]]
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; CHECK: tbb:
50+
; CHECK: br label [[JOIN]]
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; CHECK: fbb:
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; CHECK: br label [[JOIN]]
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; CHECK: join:
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; CHECK: br label [[BB3]]
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; CHECK: end:
56+
; CHECK: store i32 [[TMP8]], i32 addrspace(1)* [[DST:%[A-z0-9]*]], align 4
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; CHECK: ret void
58+
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entry:
60+
%0 = extractelement <8 x i32> %r0, i32 1
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%1 = extractelement <3 x i32> %globalSize, i32 0
62+
%2 = extractelement <3 x i32> %localSize, i32 0
63+
%3 = extractelement <3 x i32> %enqueuedLocalSize, i32 0
64+
%4 = mul i32 %3, %0
65+
%5 = zext i16 %localIdX to i32
66+
%6 = add i32 %5, %4
67+
%7 = extractelement <8 x i32> %payloadHeader, i32 0
68+
%8 = add i32 %6, %7
69+
br label %bb3
70+
71+
bb1: ; preds = %bb3, %bb1
72+
%a = phi i32 [ %b, %bb3 ], [ %ai, %bb1 ]
73+
%lc = phi i32 [ %bi, %bb3 ], [ %lc, %bb1 ]
74+
%ai = add i32 %a, 1
75+
%ac = icmp ne i32 %8, %ai
76+
%cc = icmp eq i32 %ai, %lc
77+
br i1 %cc, label %bb2, label %bb1
78+
79+
bb2: ; preds = %bb1
80+
br i1 %ac, label %tbb, label %fbb
81+
82+
bb3: ; preds = %join, %entry
83+
%b = phi i32 [ -1, %entry ], [ %bi, %join ]
84+
%bl = phi i32 [ 0, %entry ], [ %bli, %join ]
85+
%bi = add i32 %b, %2
86+
%bli = add i32 %bl, %2
87+
%bc = icmp ult i32 %bli, %1
88+
br i1 %bc, label %bb1, label %end
89+
90+
tbb: ; preds = %bb2
91+
%aaa = add i32 %1, %2
92+
br label %join
93+
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fbb: ; preds = %bb2
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br label %join
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join: ; preds = %fbb, %tbb
98+
br label %bb3
99+
100+
end: ; preds = %bb3
101+
store i32 %8, i32 addrspace(1)* %dst, align 4
102+
ret void
103+
}
104+
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; Function Attrs: nounwind readnone speculatable
106+
declare void @llvm.dbg.declare(metadata, metadata, metadata) #1
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; Function Attrs: convergent nounwind readnone
109+
declare spir_func i32 @__builtin_IB_get_local_size(i32) local_unnamed_addr #2
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; Function Attrs: convergent nounwind readnone
112+
declare spir_func i32 @__builtin_IB_get_global_size(i32) local_unnamed_addr #2
113+
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; Function Attrs: nounwind readnone speculatable
115+
declare void @llvm.dbg.value(metadata, metadata, metadata) #1
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attributes #0 = { convergent noinline nounwind optnone }
118+
attributes #1 = { nounwind readnone speculatable }
119+
attributes #2 = { convergent nounwind readnone }
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121+
!igc.functions = !{!3}
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123+
!3 = !{void (i32 addrspace(1)*, <8 x i32>, <8 x i32>, i16, i16, i16, <3 x i32>, <3 x i32>, <3 x i32>, i8*, i32)* @test, !4}
124+
!4 = !{!5, !6}
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!5 = !{!"function_type", i32 0}
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!6 = !{!"implicit_arg_desc", !7, !8, !9, !10, !11, !12}
127+
!7 = !{i32 0}
128+
!8 = !{i32 1}
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!9 = !{i32 4}
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!10 = !{i32 5}
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!11 = !{i32 12}
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!12 = !{i32 14, !13}
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!13 = !{!"explicit_arg_num", i32 0}

‎IGC/Compiler/tests/AdvCodeMotion/hoist2.ll

Lines changed: 155 additions & 0 deletions
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@@ -0,0 +1,155 @@
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;=========================== begin_copyright_notice ============================
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;
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; Copyright (C) 2022 Intel Corporation
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;
5+
; SPDX-License-Identifier: MIT
6+
;
7+
;============================ end_copyright_notice =============================
8+
;
9+
; RUN: igc_opt -adv-codemotion-cm=1 -igc-advcodemotion -S < %s | FileCheck %s
10+
; ------------------------------------------------
11+
; AdvCodeMotion
12+
; ------------------------------------------------
13+
14+
define spir_kernel void @test(i32 addrspace(1)* %dst, <8 x i32> %r0, <8 x i32> %payloadHeader, i16 %localIdX, i16 %localIdY, i16 %localIdZ, <3 x i32> %globalSize, <3 x i32> %enqueuedLocalSize, <3 x i32> %localSize, i8* %privateBase, i32 %bufferOffset) #0 {
15+
16+
; CHECK-LABEL: @test(
17+
; CHECK-NEXT: entry:
18+
; CHECK-NEXT: [[TMP0:%.*]] = extractelement <8 x i32> [[R0:%.*]], i32 1
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; CHECK-NEXT: [[TMP1:%.*]] = extractelement <3 x i32> [[GLOBALSIZE:%.*]], i32 0
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; CHECK-NEXT: [[TMP2:%.*]] = extractelement <3 x i32> [[LOCALSIZE:%.*]], i32 0
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; CHECK-NEXT: [[TMP3:%.*]] = extractelement <3 x i32> [[ENQUEUEDLOCALSIZE:%.*]], i32 0
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; CHECK-NEXT: [[TMP4:%.*]] = mul i32 [[TMP3]], [[TMP0]]
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; CHECK-NEXT: [[TMP5:%.*]] = zext i16 [[LOCALIDX:%.*]] to i32
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; CHECK-NEXT: [[TMP6:%.*]] = add i32 [[TMP5]], [[TMP4]]
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; CHECK-NEXT: [[TMP7:%.*]] = extractelement <8 x i32> [[PAYLOADHEADER:%.*]], i32 0
26+
; CHECK-NEXT: [[TMP8:%.*]] = add i32 [[TMP6]], [[TMP7]]
27+
; CHECK-NEXT: br label [[BB3:%.*]]
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; CHECK: bb1:
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; CHECK-NEXT: [[A:%.*]] = phi i32 [ [[B:%.*]], [[BB3]] ], [ [[AI:%.*]], [[BB1:%.*]] ]
30+
; CHECK-NEXT: [[LC:%.*]] = phi i32 [ [[BI:%.*]], [[BB3]] ], [ [[LC]], [[BB1]] ]
31+
; CHECK-NEXT: [[AI]] = add i32 [[A]], 1
32+
; CHECK-NEXT: [[AC:%.*]] = icmp ne i32 [[TMP8]], [[AI]]
33+
; CHECK-NEXT: [[CC:%.*]] = icmp eq i32 [[AI]], [[LC]]
34+
; CHECK-NEXT: br i1 [[CC]], label [[BB2:%.*]], label [[BB1]]
35+
; CHECK: bb2:
36+
; CHECK-NEXT: [[AAA:%.*]] = add i32 [[TMP1]], [[TMP2]]
37+
; CHECK-NEXT: [[ACC:%.*]] = icmp eq i32 [[AAA]], 0
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; CHECK-NEXT: [[TMP9:%.*]] = and i1 [[AC]], [[ACC]]
39+
; CHECK-NEXT: br i1 [[TMP9]], label [[TBB2:%.*]], label [[FBB2:%.*]]
40+
; CHECK: bb3:
41+
; CHECK-NEXT: [[B]] = phi i32 [ -1, [[ENTRY:%.*]] ], [ [[BI]], [[JOIN2:%.*]] ]
42+
; CHECK-NEXT: [[BL:%.*]] = phi i32 [ 0, [[ENTRY]] ], [ [[BLI:%.*]], [[JOIN2]] ]
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; CHECK-NEXT: [[BI]] = add i32 [[B]], [[TMP2]]
44+
; CHECK-NEXT: [[BLI]] = add i32 [[BL]], [[TMP2]]
45+
; CHECK-NEXT: [[BC:%.*]] = icmp ult i32 [[BLI]], [[TMP1]]
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; CHECK-NEXT: br i1 [[BC]], label [[BB1]], label [[END:%.*]]
47+
; CHECK: fbb2:
48+
; CHECK-NEXT: br label [[JOIN2]]
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; CHECK: tbb2:
50+
; CHECK-NEXT: [[BBB:%.*]] = add i32 [[TMP1]], [[TMP2]]
51+
; CHECK-NEXT: br label [[JOIN2]]
52+
; CHECK: join2:
53+
; CHECK-NEXT: [[J2PHI:%.*]] = phi i32 [ [[BBB]], [[TBB2]] ], [ 0, [[FBB2]] ]
54+
; CHECK-NEXT: [[ORPHI:%.*]] = phi i32 [ 1, [[TBB2]] ], [ [[TMP1]], [[FBB2]] ]
55+
; CHECK-NEXT: store i32 [[J2PHI]], i32 addrspace(1)* [[DST:%.*]], align 4
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; CHECK-NEXT: store i32 [[ORPHI]], i32 addrspace(1)* [[DST]], align 4
57+
; CHECK-NEXT: store i32 -1, i32 addrspace(1)* [[DST]], align 4
58+
; CHECK-NEXT: br label [[BB3]]
59+
; CHECK: end:
60+
; CHECK-NEXT: store i32 [[TMP8]], i32 addrspace(1)* [[DST]], align 4
61+
; CHECK-NEXT: ret void
62+
63+
entry:
64+
%0 = extractelement <8 x i32> %r0, i32 1
65+
%1 = extractelement <3 x i32> %globalSize, i32 0
66+
%2 = extractelement <3 x i32> %localSize, i32 0
67+
%3 = extractelement <3 x i32> %enqueuedLocalSize, i32 0
68+
%4 = mul i32 %3, %0
69+
%5 = zext i16 %localIdX to i32
70+
%6 = add i32 %5, %4
71+
%7 = extractelement <8 x i32> %payloadHeader, i32 0
72+
%8 = add i32 %6, %7
73+
br label %bb3
74+
75+
bb1: ; preds = %bb3, %bb1
76+
%a = phi i32 [ %b, %bb3 ], [ %ai, %bb1 ]
77+
%lc = phi i32 [ %bi, %bb3 ], [ %lc, %bb1 ]
78+
%ai = add i32 %a, 1
79+
%ac = icmp ne i32 %8, %ai
80+
%cc = icmp eq i32 %ai, %lc
81+
br i1 %cc, label %bb2, label %bb1
82+
83+
bb2: ; preds = %bb1
84+
br i1 %ac, label %bb4, label %fbb
85+
86+
bb3: ; preds = %join, %entry
87+
%b = phi i32 [ -1, %entry ], [ %bi, %join ]
88+
%bl = phi i32 [ 0, %entry ], [ %bli, %join ]
89+
%bi = add i32 %b, %2
90+
%bli = add i32 %bl, %2
91+
%bc = icmp ult i32 %bli, %1
92+
br i1 %bc, label %bb1, label %end
93+
94+
bb4: ; preds = %bb2
95+
%aaa = add i32 %1, %2
96+
%acc = icmp eq i32 %aaa, 0
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br i1 %acc, label %tbb2, label %fbb2
98+
99+
fbb: ; preds = %bb2
100+
br label %join
101+
102+
fbb2: ; preds = %bb4
103+
br label %join2
104+
105+
tbb2: ; preds = %bb4
106+
%bbb = add i32 %1, %2
107+
br label %join2
108+
109+
join2: ; preds = %tbb2, %fbb2
110+
%j2phi = phi i32 [ %bbb, %tbb2 ], [ 0, %fbb2 ]
111+
%orphi = phi i32 [ 1, %tbb2 ], [ 0, %fbb2 ]
112+
store i32 %j2phi, i32 addrspace(1)* %dst, align 4
113+
%oropt = or i32 %1, %orphi
114+
store i32 %oropt, i32 addrspace(1)* %dst, align 4
115+
br label %join
116+
117+
join: ; preds = %join2, %fbb
118+
%jphi = phi i32 [ -1, %join2 ], [ 0, %fbb ]
119+
store i32 %jphi, i32 addrspace(1)* %dst, align 4
120+
br label %bb3
121+
122+
end: ; preds = %bb3
123+
store i32 %8, i32 addrspace(1)* %dst, align 4
124+
ret void
125+
}
126+
127+
; Function Attrs: nounwind readnone speculatable
128+
declare void @llvm.dbg.declare(metadata, metadata, metadata) #1
129+
130+
; Function Attrs: convergent nounwind readnone
131+
declare spir_func i32 @__builtin_IB_get_local_size(i32) local_unnamed_addr #2
132+
133+
; Function Attrs: convergent nounwind readnone
134+
declare spir_func i32 @__builtin_IB_get_global_size(i32) local_unnamed_addr #2
135+
136+
; Function Attrs: nounwind readnone speculatable
137+
declare void @llvm.dbg.value(metadata, metadata, metadata) #1
138+
139+
attributes #0 = { convergent noinline nounwind optnone }
140+
attributes #1 = { nounwind readnone speculatable }
141+
attributes #2 = { convergent nounwind readnone }
142+
143+
!igc.functions = !{!0}
144+
145+
!0 = !{void (i32 addrspace(1)*, <8 x i32>, <8 x i32>, i16, i16, i16, <3 x i32>, <3 x i32>, <3 x i32>, i8*, i32)* @test, !1}
146+
!1 = !{!2, !3}
147+
!2 = !{!"function_type", i32 0}
148+
!3 = !{!"implicit_arg_desc", !4, !5, !6, !7, !8, !9}
149+
!4 = !{i32 0}
150+
!5 = !{i32 1}
151+
!6 = !{i32 4}
152+
!7 = !{i32 5}
153+
!8 = !{i32 12}
154+
!9 = !{i32 14, !10}
155+
!10 = !{!"explicit_arg_num", i32 0}

‎IGC/Compiler/tests/AdvMemOpt/basic.ll

Lines changed: 68 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,68 @@
1+
;=========================== begin_copyright_notice ============================
2+
;
3+
; Copyright (C) 2022 Intel Corporation
4+
;
5+
; SPDX-License-Identifier: MIT
6+
;
7+
;============================ end_copyright_notice =============================
8+
;
9+
; RUN: igc_opt -debugify -igc-advmemopt -check-debugify -S < %s 2>&1 | FileCheck %s
10+
; ------------------------------------------------
11+
; AdvMemOpt
12+
; ------------------------------------------------
13+
14+
; Debug-info related check
15+
; CHECK-NOT: WARNING
16+
; CHECK: CheckModuleDebugify: PASS
17+
18+
define void @test(i32 %a, i32* %b) {
19+
; CHECK-LABEL: @test(
20+
; CHECK: entry:
21+
; CHECK: [[TMP0:%[A-z0-9]*]] = icmp slt i32 [[A:%[A-z0-9]*]], 13
22+
; CHECK: br i1 [[TMP0]], label [[BB:%[A-z0-9]*]], label [[END:%[A-z0-9]*]]
23+
; CHECK: bb:
24+
; CHECK: [[TMP1:%[A-z0-9]*]] = phi i32 [ 0, [[ENTRY:%[A-z0-9]*]] ], [ [[TMP3:%[A-z0-9]*]], [[BB1:%[A-z0-9]*]] ]
25+
; CHECK: [[TMP2:%[A-z0-9]*]] = load i32, i32* [[B:%[A-z0-9]*]], align 4{{.*}}, !uniform [[TRUE_MD:![0-9]*]]
26+
; CHECK: [[C:%[A-z0-9]*]] = load i32, i32* [[B]], align 4{{.*}}, !uniform [[TRUE_MD]]
27+
; CHECK: br label [[BB1]]
28+
; CHECK: bb1:
29+
; CHECK: [[TMP3]] = add i32 [[TMP1]], [[TMP2]]
30+
; CHECK: [[TMP4:%[A-z0-9]*]] = add i32 [[C]], [[TMP3]]
31+
; CHECK: [[TMP5:%[A-z0-9]*]] = icmp slt i32 [[TMP3]], [[A]]
32+
; CHECK: br i1 [[TMP5]], label [[BB]], label [[END]]
33+
; CHECK: end:
34+
; CHECK: [[TMP6:%[A-z0-9]*]] = phi i32 [ [[A]], [[ENTRY]] ], [ [[TMP4]], [[BB1]] ]
35+
; CHECK: store i32 [[TMP6]], i32* [[B]]
36+
; CHECK: ret void
37+
;
38+
entry:
39+
%0 = icmp slt i32 %a, 13
40+
br i1 %0, label %bb, label %end
41+
42+
bb: ; preds = %bb1, %entry
43+
%1 = phi i32 [ 0, %entry ], [ %3, %bb1 ]
44+
%2 = load i32, i32* %b, align 4, !uniform !4
45+
br label %bb1
46+
47+
bb1: ; preds = %bb
48+
%c = load i32, i32* %b, align 4, !uniform !4
49+
%3 = add i32 %1, %2
50+
%4 = add i32 %c, %3
51+
%5 = icmp slt i32 %3, %a
52+
br i1 %5, label %bb, label %end
53+
54+
end: ; preds = %bb1, %entry
55+
%6 = phi i32 [ %a, %entry ], [ %4, %bb1 ]
56+
store i32 %6, i32* %b
57+
ret void
58+
}
59+
60+
; CHECK: [[TRUE_MD]] = !{i1 true}
61+
62+
!igc.functions = !{!0}
63+
64+
!0 = !{void (i32, i32*)* @test, !1}
65+
!1 = !{!2, !3}
66+
!2 = !{!"function_type", i32 0}
67+
!3 = !{!"implicit_arg_desc"}
68+
!4 = !{i1 true}

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