Add reg key EnableOneStepElf. Fix a bug

where some Gen offsets were missing in debug_ranges section.

Change-Id: I17daa9d265d9b2218a195d50153d1924a03060ba

Author: pratikashar

IGC/Compiler/DebugInfo/VISAModule.cpp

@@ -768,6 +768,16 @@ std::vector<std::pair<unsigned int, unsigned int>> VISAModule::getGenISARange(co
     std::vector<std::pair<unsigned int, unsigned int>> GenISARange;
     bool endNextInst = false;
 
+    auto getNextInst = [](const llvm::Instruction* start)
+    {
+        // Return consecutive instruction in llvm IR.
+        // Iterate to next BB if required.
+        if (start->getNextNode())
+            return start->getNextNode();
+        else
+            return &(start->getParent()->getNextNode()->front());
+    };
+
     while (1)
     {
         if (!start || !end || endNextInst)
@@ -780,7 +790,7 @@ std::vector<std::pair<unsigned int, unsigned int>> VISAModule::getGenISARange(co
         InstInfoMap::const_iterator itr = m_instInfoMap.find(start);
         if (itr == m_instInfoMap.end())
         {
-            start = start->getNextNode();
+            start = getNextInst(start);
             continue;
         }
         auto startVISAOffset = itr->second.m_offset;
@@ -815,7 +825,7 @@ std::vector<std::pair<unsigned int, unsigned int>> VISAModule::getGenISARange(co
             }
         }
 
-        start = start->getNextNode();
+        start = getNextInst(start);
     }
 
     class Comp

IGC/Compiler/DebugInfo/VISAModule.hpp

@@ -332,7 +332,8 @@ class VISAModule
     {
         auto n = new VISAModule(s);
 
-        if (n->m_pShader->GetContext()->m_DriverInfo.SupportElfFormat())
+        if (n->m_pShader->GetContext()->m_DriverInfo.SupportElfFormat() ||
+            IGC_GET_FLAG_VALUE(EnableOneStepElf))
         {
             n->isDirectElfInput = true;
         }

IGC/common/igc_flags.def

@@ -310,6 +310,7 @@ DECLARE_IGC_REGKEY(bool, ForceSubroutineForEmulation,   false,  "Force subroutin
 DECLARE_IGC_REGKEY(int, ByPassAllocaSizeHeuristic,   0,  "Force some Alloca to pass the pressure heuristic until the given size")
 DECLARE_IGC_REGKEY(DWORD, MemOptWindowSize,   150,  "Change the size of the window in which we allow load/stores to be coalesced. We keep it limited in order to avoid creating long liveranges. Default value is 150")
 DECLARE_IGC_REGKEY(bool, ForceNoFP64bRegioning, false, "force regioning rules for FP and 64b FPU instructions")
+DECLARE_IGC_REGKEY(bool, EnableOneStepElf, false, "Enable generation of direct elf mapping src->Gen ISA")
 
 DECLARE_IGC_GROUP("Generating precompiled headers")
 DECLARE_IGC_REGKEY(bool, ApplyConservativeRastWAHeader, true,