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fangliu2020igcbot
fangliu2020
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igcbot
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[IGC vISA] Added native bf16 support interfaces
Added native bf16 support interfaces
1 parent 02a1e3f commit d9f3a71

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10 files changed

+83
-25
lines changed

10 files changed

+83
-25
lines changed

‎visa/BuildIRImpl.cpp

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -2126,7 +2126,9 @@ G4_MathOp IR_Builder::Get_MathFuncCtrl(ISA_Opcode op, G4_Type type) {
21262126
case ISA_INV:
21272127
return MATH_INV;
21282128
case ISA_DIV:
2129-
return IS_FTYPE(type) || IS_HFTYPE(type) ? MATH_FDIV : MATH_INT_DIV_QUOT;
2129+
return (IS_FTYPE(type) || IS_HFTYPE(type) || IS_BFTYPE(type))
2130+
? MATH_FDIV
2131+
: MATH_INT_DIV_QUOT;
21302132
case ISA_EXP:
21312133
return MATH_EXP;
21322134
default:

‎visa/CISA.l

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -938,6 +938,12 @@ type[ ]*=[ ]*(ud|d|uw|w|ub|b|df|f|bool|uq|q|UD|D|UW|W|UB|B|DF|F|Bool|BOOL|UQ|Q|h
938938
return HFTYPE;
939939
}
940940

941+
:(bf|BF) {
942+
TRACE("** BFTYPE");
943+
CISAlval.type = str2type(yytext, yyleng);
944+
return BFTYPE;
945+
}
946+
941947
:(ud|d|uw|w|ub|b|bool|UD|D|UW|W|UB|B|BOOL|Bool|q|uq|Q|UQ|hf|HF) {
942948
TRACE("** DATA TYPE");
943949
CISAlval.type = str2type(yytext, yyleng);

‎visa/CISA.y

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -340,6 +340,7 @@ std::vector<attr_gen_struct*> AttrOptVar;
340340
%token <type> DFTYPE // :df
341341
%token <type> FTYPE // :f
342342
%token <type> HFTYPE // :hf
343+
%token <type> BFTYPE // :bf
343344
%token <type> VTYPE // :v and vf
344345
%token <cond_mod> COND_MOD // .ne .ge ...
345346

@@ -2986,6 +2987,7 @@ DataType: DataTypeIntOrVector
29862987
| DFTYPE
29872988
| FTYPE
29882989
| HFTYPE
2990+
| BFTYPE
29892991
DataTypeIntOrVector:
29902992
ITYPE
29912993
| VTYPE

‎visa/Common_ISA.h

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -629,6 +629,12 @@ struct CISA_INST {
629629
VISA_EMask_Ctrl getExecMask() const {
630630
return (VISA_EMask_Ctrl)(execsize >> 4);
631631
}
632+
bool isMath() const{
633+
return (opcode == ISA_COS || opcode == ISA_DIV || opcode == ISA_EXP ||
634+
opcode == ISA_INV || opcode == ISA_LOG || opcode == ISA_POW ||
635+
opcode == ISA_RSQRT || opcode == ISA_SIN || opcode == ISA_SQRT ||
636+
opcode == ISA_SIN);
637+
}
632638
};
633639

634640
extern const char *CISAAtomicOpNames[];

‎visa/G4_IR.cpp

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -383,7 +383,8 @@ G4_Type G4_INST::getExecType2() const {
383383
if (!src)
384384
continue;
385385
G4_Type srcType = srcs[i]->getType();
386-
if (builder.hasBFMixMode() && srcType == Type_BF) {
386+
if (builder.hasBFMixMode() && srcType == Type_BF &&
387+
!builder.supportPureBF()) {
387388
execType = Type_F;
388389
} else if (isLowPrecisionFloatTy(srcType) &&
389390
TypeSize(srcType) >= TypeSize(execType)) {

‎visa/G4_IR.hpp

Lines changed: 18 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -923,6 +923,24 @@ class G4_INST {
923923

924924
const IR_Builder &getBuilder() const { return builder; }
925925

926+
bool isPureBFInst() const {
927+
G4_Operand *dst = getDst();
928+
if (!dst || dst->getType() != Type_BF)
929+
return false;
930+
for (int i = 0, numSrcs = getNumSrc(); i < numSrcs; i++) {
931+
auto src = getSrc(i);
932+
if (src && src->getType() != Type_BF)
933+
return false;
934+
}
935+
return true;
936+
}
937+
938+
bool canSupportPureBF() const {
939+
return (op == G4_mov || op == G4_add || op == G4_sel || op == G4_cmp ||
940+
op == G4_csel || op == G4_cmpn || op == G4_mul || op == G4_mad ||
941+
op == G4_math);
942+
}
943+
926944
private:
927945
// use inheritDIFrom() instead
928946
void setLocation(MDLocation *loc) { setMetadata(Metadata::InstLoc, loc); }

‎visa/G4_Opcode.h

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -22,6 +22,7 @@ SPDX-License-Identifier: MIT
2222
#define G4_DSIZE 4 // 4 bytes 32 bits
2323
#define IS_FTYPE(x) ((x) == Type_F)
2424
#define IS_HFTYPE(x) ((x) == Type_HF)
25+
#define IS_BFTYPE(x) ((x) == Type_BF)
2526
#define IS_DFTYPE(x) ((x) == Type_DF || (x) == Type_NF)
2627
#define IS_DTYPE(x) ((x) == Type_D || (x) == Type_UD)
2728
#define IS_VINTTYPE(x) ((x) == Type_V || (x) == Type_UV)

‎visa/HWCaps.inc

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -797,4 +797,8 @@ bool noSrc0Src1OverlapSend() const {
797797
bool WARLocalization() const {
798798
return false;
799799
}
800+
801+
bool supportPureBF() const {
802+
return false;
803+
}
800804
// end HW capabilities

‎visa/IsaDescription.cpp

Lines changed: 23 additions & 23 deletions
Original file line numberDiff line numberDiff line change
@@ -233,8 +233,8 @@ VISA_INST_Desc CISA_INST_table[ISA_NUM_OPCODE] = {
233233
{OPND_EXECSIZE, ISA_TYPE_UB, 0},
234234
{OPND_PRED, ISA_TYPE_UW, 0},
235235
{OPND_VECTOR_DST_G_I, TYPE_INTEGER | TYPE_FLOAT, SAT_FLOAT_ONLY},
236-
{OPND_VECTOR_SRC_G_I_IMM_AO, TYPE_INTEGER | TYPE_FLOAT_HF, 0},
237-
{OPND_VECTOR_SRC_G_I_IMM_AO, TYPE_INTEGER | TYPE_FLOAT_HF, 0},
236+
{OPND_VECTOR_SRC_G_I_IMM_AO, TYPE_INTEGER | TYPE_FLOAT_ALL, 0},
237+
{OPND_VECTOR_SRC_G_I_IMM_AO, TYPE_INTEGER | TYPE_FLOAT_ALL, 0},
238238
},
239239

240240
},
@@ -322,8 +322,8 @@ VISA_INST_Desc CISA_INST_table[ISA_NUM_OPCODE] = {
322322
{
323323
{OPND_EXECSIZE, ISA_TYPE_UB, 0},
324324
{OPND_PRED, ISA_TYPE_UW, 0},
325-
{OPND_VECTOR_DST_G_I, TYPE_FLOAT_HF, SAT_C | HORIZON_STRIDE_1},
326-
{OPND_VECTOR_SRC_G_I_IMM_AO, TYPE_FLOAT_HF, HORIZON_STRIDE_1},
325+
{OPND_VECTOR_DST_G_I, TYPE_FLOAT_ALL, SAT_C | HORIZON_STRIDE_1},
326+
{OPND_VECTOR_SRC_G_I_IMM_AO, TYPE_FLOAT_ALL, HORIZON_STRIDE_1},
327327
},
328328

329329
},
@@ -375,8 +375,8 @@ VISA_INST_Desc CISA_INST_table[ISA_NUM_OPCODE] = {
375375
{
376376
{OPND_EXECSIZE, ISA_TYPE_UB, 0},
377377
{OPND_PRED, ISA_TYPE_UW, 0},
378-
{OPND_VECTOR_DST_G_I, TYPE_FLOAT_HF, SAT_C},
379-
{OPND_VECTOR_SRC_G_I_IMM_AO, TYPE_FLOAT_HF, 0},
378+
{OPND_VECTOR_DST_G_I, TYPE_FLOAT_ALL, SAT_C},
379+
{OPND_VECTOR_SRC_G_I_IMM_AO, TYPE_FLOAT_ALL, 0},
380380
},
381381

382382
},
@@ -485,9 +485,9 @@ VISA_INST_Desc CISA_INST_table[ISA_NUM_OPCODE] = {
485485
{
486486
{OPND_EXECSIZE, ISA_TYPE_UB, 0},
487487
{OPND_PRED, ISA_TYPE_UW, 0},
488-
{OPND_VECTOR_DST_G_I, TYPE_FLOAT_HF, SAT_C},
489-
{OPND_VECTOR_SRC_G_I_IMM_AO, TYPE_FLOAT_HF, 0},
490-
{OPND_VECTOR_SRC_G_I_IMM_AO, TYPE_FLOAT_HF, 0},
488+
{OPND_VECTOR_DST_G_I, TYPE_FLOAT_ALL, SAT_C},
489+
{OPND_VECTOR_SRC_G_I_IMM_AO, TYPE_FLOAT_ALL, 0},
490+
{OPND_VECTOR_SRC_G_I_IMM_AO, TYPE_FLOAT_ALL, 0},
491491
},
492492

493493
},
@@ -590,8 +590,8 @@ VISA_INST_Desc CISA_INST_table[ISA_NUM_OPCODE] = {
590590
{
591591
{OPND_EXECSIZE, ISA_TYPE_UB, 0},
592592
{OPND_PRED, ISA_TYPE_UW, 0},
593-
{OPND_VECTOR_DST_G_I, TYPE_FLOAT_HF, SAT_C},
594-
{OPND_VECTOR_SRC_G_I_IMM_AO, TYPE_FLOAT_HF, 0},
593+
{OPND_VECTOR_DST_G_I, TYPE_FLOAT_ALL, SAT_C},
594+
{OPND_VECTOR_SRC_G_I_IMM_AO, TYPE_FLOAT_ALL, 0},
595595
},
596596

597597
},
@@ -607,8 +607,8 @@ VISA_INST_Desc CISA_INST_table[ISA_NUM_OPCODE] = {
607607
{
608608
{OPND_EXECSIZE, ISA_TYPE_UB, 0},
609609
{OPND_PRED, ISA_TYPE_UW, 0},
610-
{OPND_VECTOR_DST_G_I, TYPE_FLOAT_HF, SAT_C},
611-
{OPND_VECTOR_SRC_G_I_IMM_AO, TYPE_FLOAT_HF, 0},
610+
{OPND_VECTOR_DST_G_I, TYPE_FLOAT_ALL, SAT_C},
611+
{OPND_VECTOR_SRC_G_I_IMM_AO, TYPE_FLOAT_ALL, 0},
612612
},
613613

614614
},
@@ -624,8 +624,8 @@ VISA_INST_Desc CISA_INST_table[ISA_NUM_OPCODE] = {
624624
{
625625
{OPND_EXECSIZE, ISA_TYPE_UB, 0},
626626
{OPND_PRED, ISA_TYPE_UW, 0},
627-
{OPND_VECTOR_DST_G_I, TYPE_FLOAT_HF, SAT_C},
628-
{OPND_VECTOR_SRC_G_I_IMM_AO, TYPE_FLOAT_HF, 0},
627+
{OPND_VECTOR_DST_G_I, TYPE_FLOAT_ALL, SAT_C},
628+
{OPND_VECTOR_SRC_G_I_IMM_AO, TYPE_FLOAT_ALL, 0},
629629
},
630630

631631
},
@@ -641,8 +641,8 @@ VISA_INST_Desc CISA_INST_table[ISA_NUM_OPCODE] = {
641641
{
642642
{OPND_EXECSIZE, ISA_TYPE_UB, 0},
643643
{OPND_PRED, ISA_TYPE_UW, 0},
644-
{OPND_VECTOR_DST_G_I, TYPE_FLOAT_HF, SAT_C},
645-
{OPND_VECTOR_SRC_G_I_IMM_AO, TYPE_FLOAT_HF, 0},
644+
{OPND_VECTOR_DST_G_I, TYPE_FLOAT_ALL, SAT_C},
645+
{OPND_VECTOR_SRC_G_I_IMM_AO, TYPE_FLOAT_ALL, 0},
646646
},
647647

648648
},
@@ -658,8 +658,8 @@ VISA_INST_Desc CISA_INST_table[ISA_NUM_OPCODE] = {
658658
{
659659
{OPND_EXECSIZE, ISA_TYPE_UB, 0},
660660
{OPND_PRED, ISA_TYPE_UW, 0},
661-
{OPND_VECTOR_DST_G_I, TYPE_FLOAT_HF, SAT_C},
662-
{OPND_VECTOR_SRC_G_I_IMM_AO, TYPE_FLOAT_HF, 0},
661+
{OPND_VECTOR_DST_G_I, TYPE_FLOAT_ALL, SAT_C},
662+
{OPND_VECTOR_SRC_G_I_IMM_AO, TYPE_FLOAT_ALL, 0},
663663
},
664664

665665
},
@@ -2454,10 +2454,10 @@ VISA_INST_Desc CISA_INST_table[ISA_NUM_OPCODE] = {
24542454
6,
24552455
SAME_DATA_TYPE,
24562456
{{OPND_EXECSIZE, ISA_TYPE_UB, 0},
2457-
{OPND_DST_GEN, ISA_TYPE_D | ISA_TYPE_UD | ISA_TYPE_F, GRF_ALIGNED},
2458-
{OPND_SRC_GEN, ISA_TYPE_D | ISA_TYPE_UD | ISA_TYPE_F, GRF_ALIGNED},
2459-
{OPND_SRC_GEN, ISA_TYPE_D | ISA_TYPE_UD, GRF_ALIGNED},
2460-
{OPND_SRC_GEN, ISA_TYPE_D | ISA_TYPE_UD, GRF_ALIGNED},
2457+
{OPND_DST_GEN, ISA_TYPE_D | ISA_TYPE_UD | TYPE_FLOAT_ALL, GRF_ALIGNED},
2458+
{OPND_SRC_GEN, ISA_TYPE_D | ISA_TYPE_UD | TYPE_FLOAT_ALL, GRF_ALIGNED},
2459+
{OPND_SRC_GEN, ISA_TYPE_D | ISA_TYPE_UD | ISA_TYPE_DF, GRF_ALIGNED},
2460+
{OPND_SRC_GEN, ISA_TYPE_D | ISA_TYPE_UD | ISA_TYPE_DF, GRF_ALIGNED},
24612461
{OPND_OTHER, ISA_TYPE_UD, 0}},
24622462
},
24632463

‎visa/IsaVerification.cpp

Lines changed: 18 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -3398,6 +3398,17 @@ void vISAVerifier::verifyBFMixedMode(const CISA_INST *inst) {
33983398
case ISA_SEL:
33993399
case ISA_CMP:
34003400
break;
3401+
case ISA_COS:
3402+
case ISA_DIV:
3403+
case ISA_EXP:
3404+
case ISA_INV:
3405+
case ISA_LOG:
3406+
case ISA_POW:
3407+
case ISA_RSQRT:
3408+
case ISA_SIN:
3409+
case ISA_SQRT:
3410+
if (irBuilder->supportPureBF())
3411+
break;
34013412
default:
34023413
REPORT_INSTRUCTION(options, false,
34033414
"BF opnd is not allowed on this instruction");
@@ -3416,6 +3427,10 @@ void vISAVerifier::verifyBFMixedMode(const CISA_INST *inst) {
34163427
REPORT_INSTRUCTION(options,
34173428
(dstType == ISA_TYPE_F || dstType == ISA_TYPE_BF),
34183429
"Dst opnd in BF mixed mode should be either BF or F");
3430+
if (irBuilder->supportPureBF() && inst->isMath())
3431+
REPORT_INSTRUCTION(
3432+
options, (dstType == ISA_TYPE_BF),
3433+
"Math instructions must be pure BF mode");
34193434
}
34203435
} else {
34213436
// cmp's 1st opnd is cmp relop
@@ -3426,6 +3441,9 @@ void vISAVerifier::verifyBFMixedMode(const CISA_INST *inst) {
34263441
REPORT_INSTRUCTION(options,
34273442
(srcType == ISA_TYPE_F || srcType == ISA_TYPE_BF),
34283443
"Src opnd in BF mixed mode should be either BF or F");
3444+
if (irBuilder->supportPureBF() && inst->isMath())
3445+
REPORT_INSTRUCTION(options, (srcType == ISA_TYPE_BF),
3446+
"Math instructions must be pure BF mode");
34293447
}
34303448
return;
34313449
}

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