Fixed warning from statical code analizer

.

Author: igorban-intel

IGC/VectorCompiler/igcdeps/include/vc/igcdeps/cmc.h

@@ -41,11 +41,13 @@ class CMKernel {
 
   explicit CMKernel(const PLATFORM &platform);
   ~CMKernel();
+  CMKernel(const CMKernel &) = delete;
+  CMKernel &operator=(const CMKernel &) = delete;
 
   PLATFORM m_platform;
   IGC::SOpenCLKernelInfo m_kernelInfo;
   IGC::COCLBTILayout m_btiLayout;
-  uint32_t m_GRFSizeInBytes;
+  uint32_t m_GRFSizeInBytes = 0;
   bool m_SupportsDebugging = false;
 
   // getter for convenience

IGC/VectorCompiler/include/vc/Support/BackendConfig.h

@@ -233,8 +233,8 @@ class GenXBackendConfig : public ImmutablePass {
 
 public:
   GenXBackendConfig();
-  explicit GenXBackendConfig(GenXBackendOptions OptionsIn,
-                             GenXBackendData DataIn);
+  explicit GenXBackendConfig(GenXBackendOptions &&OptionsIn,
+                             GenXBackendData &&DataIn);
 
   // Return whether regalloc results should be printed.
   bool enableRegAllocDump() const { return Options.DumpRegAlloc; }

IGC/VectorCompiler/include/vc/Utils/General/InstRebuilder.h

@@ -1,6 +1,6 @@
 /*========================== begin_copyright_notice ============================
 
-Copyright (C) 2021 Intel Corporation
+Copyright (C) 2021-2023 Intel Corporation
 
 SPDX-License-Identifier: MIT
 
@@ -153,7 +153,7 @@ class InstructionRebuilder {
   InstructionRebuilder(RebuildInfo ToRebuildIn,
                        IsSpecialInstFunc IsSpecialInstIn,
                        CreateSpecialInstFunc CreateSpecialInstIn)
-      : ToRebuild{ToRebuildIn}, IsSpecialInst{IsSpecialInstIn},
+      : ToRebuild{std::move(ToRebuildIn)}, IsSpecialInst{IsSpecialInstIn},
         CreateSpecialInst{CreateSpecialInstIn} {}
 
   void rebuild() && {
@@ -203,14 +203,14 @@ class InstructionRebuilder {
     CurInst =
         std::accumulate(First, LastUse, std::move(CurInst),
                         [this](InstToRebuild Inst, const UseToRebuild &Use) {
-                          return appendOperand(Inst, Use);
+                          return appendOperand(std::move(Inst), Use);
                         });
     return {CurInst, LastUse};
   }
 
   // Appends operand/use from \p CurUse to \p InstInfo.
   // Returns updated \p InstInfo.
-  InstToRebuild appendOperand(InstToRebuild InstInfo,
+  InstToRebuild appendOperand(InstToRebuild &&InstInfo,
                               const UseToRebuild &CurUse) {
     IGC_ASSERT_MESSAGE(InstInfo.User == CurUse.User,
                        "trying to append a wrong use with wrong user");

IGC/VectorCompiler/lib/GenXCodeGen/ConstantEncoder.cpp

@@ -1,6 +1,6 @@
 /*========================== begin_copyright_notice ============================
 
-Copyright (C) 2021 Intel Corporation
+Copyright (C) 2021-2023 Intel Corporation
 
 SPDX-License-Identifier: MIT
 
@@ -28,7 +28,8 @@ encodeConstExprImpl(const llvm::GEPOperator &GEP, const DataLayout &DL) {
   bool Success = GEP.accumulateConstantOffset(DL, Offset);
   IGC_ASSERT_MESSAGE(Success,
                      "Offset must be constant for GEP constant expression");
-  return {Data + Offset, Relocs};
+  Data += Offset;
+  return {std::move(Data), Relocs};
 }
 
 static std::pair<APInt, std::vector<vISA::ZERelocEntry>>

IGC/VectorCompiler/lib/GenXCodeGen/FunctionGroup.h

@@ -1,6 +1,6 @@
 /*========================== begin_copyright_notice ============================
 
-Copyright (C) 2017-2021 Intel Corporation
+Copyright (C) 2017-2023 Intel Corporation
 
 SPDX-License-Identifier: MIT
 
@@ -182,6 +182,9 @@ class FunctionGroupAnalysis : public ModulePass {
   static char ID;
   explicit FunctionGroupAnalysis() : ModulePass(ID) {}
   ~FunctionGroupAnalysis() { clear(); }
+  FunctionGroupAnalysis(const FunctionGroupAnalysis &) = delete;
+  FunctionGroupAnalysis &operator=(const FunctionGroupAnalysis &) = delete;
+
   StringRef getPassName() const override { return "function group analysis"; }
   // runOnModule : does almost nothing
   bool runOnModule(Module &ArgM) override {
@@ -439,6 +442,9 @@ class DominatorTreeGroupWrapperPass
 public:
   DominatorTreeGroupWrapperPass() {}
   ~DominatorTreeGroupWrapperPass() { releaseMemory(); }
+  DominatorTreeGroupWrapperPass(const DominatorTreeGroupWrapperPass &) = delete;
+  DominatorTreeGroupWrapperPass &
+  operator=(const DominatorTreeGroupWrapperPass &) = delete;
 
   DominatorTree *getDomTree(Function *F) { return DTs[F]; }
 
@@ -471,6 +477,9 @@ class LoopInfoGroupWrapperPass : public FGPassImplInterface,
 public:
   LoopInfoGroupWrapperPass() {}
   ~LoopInfoGroupWrapperPass() { releaseMemory(); }
+  LoopInfoGroupWrapperPass(const LoopInfoGroupWrapperPass &) = delete;
+  LoopInfoGroupWrapperPass &
+  operator=(const LoopInfoGroupWrapperPass &) = delete;
 
   LoopInfo *getLoopInfo(Function *F) { return LIs[F]; }
   const DominatorTree &getDomTree();

IGC/VectorCompiler/lib/GenXCodeGen/GenXAddressCommoning.cpp

@@ -1,6 +1,6 @@
 /*========================== begin_copyright_notice ============================
 
-Copyright (C) 2017-2022 Intel Corporation
+Copyright (C) 2017-2023 Intel Corporation
 
 SPDX-License-Identifier: MIT
 
@@ -918,7 +918,7 @@ bool GenXAddressCommoning::vectorizeAddrsFromOneVector(
   Type *FirstType = Extracts[0].Addr->getOperand(0)->getType();
   IGC_ASSERT(FirstType);
 
-  for (auto e : Extracts) {
+  for (auto &e : Extracts) {
     Type *Tp = e.Addr->getOperand(0)->getType();
     if (ConvertWholeRegion && (Tp != FirstType))
       return false;

IGC/VectorCompiler/lib/GenXCodeGen/GenXAggregatePseudoLowering.cpp

@@ -1,6 +1,6 @@
 /*========================== begin_copyright_notice ============================
 
-Copyright (C) 2020-2021 Intel Corporation
+Copyright (C) 2020-2023 Intel Corporation
 
 SPDX-License-Identifier: MIT
 
@@ -399,7 +399,7 @@ static std::vector<Instruction *>
 createSplitInsts(Instruction &Inst, const SplitOpsMap &SplitOps,
                  const std::vector<IdxListType> &IdxLists) {
   std::vector<Instruction *> NewInsts;
-  for (auto IdxList : enumerate(IdxLists)) {
+  for (auto &IdxList : enumerate(IdxLists)) {
     auto NewOps =
         createSplitInstOperands(IdxList.index(), Inst.operands(), SplitOps);
     NewInsts.push_back(createSplitInst(Inst, NewOps, IdxList.value()));

IGC/VectorCompiler/lib/GenXCodeGen/GenXAlignmentInfo.h

@@ -1,6 +1,6 @@
 /*========================== begin_copyright_notice ============================
 
-Copyright (C) 2017-2021 Intel Corporation
+Copyright (C) 2017-2023 Intel Corporation
 
 SPDX-License-Identifier: MIT
 
@@ -9,24 +9,26 @@ SPDX-License-Identifier: MIT
 //
 /// genx::AlignmentInfo : alignment information
 /// -------------------------------------------
-/// 
+///
 /// AlignmentInfo is a cache of information on the alignment of instruction
 /// values in a function. It does not persist between passes.
 ///
-/// A pass that needs alignment information constructs an AlignmentInfo at 
+/// A pass that needs alignment information constructs an AlignmentInfo at
 /// the start of the pass, and then calls the ``get`` method each time it wants
-/// alignment information for a particular instruction value. AlignmentInfo 
-/// calculates it if it is not already in its cache, which probably involves 
-/// also calculating the alignment of other instructions that the given one 
+/// alignment information for a particular instruction value. AlignmentInfo
+/// calculates it if it is not already in its cache, which probably involves
+/// also calculating the alignment of other instructions that the given one
 /// depends on.
 ///
-/// This cacheing and lazy calculation is done instead of having a separate analysis
-/// pass because alignment is needed for only a small subset of values in a function.
+/// This cacheing and lazy calculation is done instead of having a separate
+/// analysis pass because alignment is needed for only a small subset of values
+/// in a function.
 ///
 /// The alignment is returned as an *Alignment* object with three fields:
-/// *ConstBits*, if ConstBits is not 0x7fffffff, alignment is a known bit-pattern,
-/// otherwise *LogAlign* and *ExtraBits* (where 0 <= ExtraBits < (1 << LogAlign)),
-/// stating that the value is known to be A << LogAlign | ExtraBits for some A.
+/// *ConstBits*, if ConstBits is not 0x7fffffff, alignment is a known
+/// bit-pattern, otherwise *LogAlign* and *ExtraBits* (where 0 <= ExtraBits < (1
+/// << LogAlign)), stating that the value is known to be A << LogAlign |
+/// ExtraBits for some A.
 ///
 /// For a vector value, the alignment information is for element 0.
 ///
@@ -68,19 +70,6 @@ class Alignment {
   Alignment(unsigned C);
   // Constructor given Constant.
   Alignment(Constant *C);
-  // Copy-constructor
-  Alignment(const Alignment& Rhs) {
-    LogAlign = Rhs.LogAlign;
-    ExtraBits = Rhs.ExtraBits;
-    ConstBits = Rhs.ConstBits;
-  }
-  // Copy-operator
-  Alignment& operator=(const Alignment &Rhs) {
-    LogAlign = Rhs.LogAlign;
-    ExtraBits = Rhs.ExtraBits;
-    ConstBits = Rhs.ConstBits;
-    return *this;
-  }
 
   // Get an unknown alignment
   static Alignment getUnknown() { return Alignment(0, 0); }

IGC/VectorCompiler/lib/GenXCodeGen/GenXArgIndirection.cpp

@@ -1,6 +1,6 @@
 /*========================== begin_copyright_notice ============================
 
-Copyright (C) 2017-2022 Intel Corporation
+Copyright (C) 2017-2023 Intel Corporation
 
 SPDX-License-Identifier: MIT
 
@@ -305,13 +305,20 @@ class SubroutineArg {
   Function *F = nullptr;
   Function *NewFunc = nullptr;
 public:
-  Argument *AddressArgument;
+  Argument *AddressArgument = nullptr;
   SubroutineArg(GenXArgIndirection *Pass, LiveRange *ArgLR, Argument *Arg)
     : Pass(Pass), ArgLR(ArgLR), Arg(Arg), F(Arg->getParent()), NewFunc(nullptr) {}
   ~SubroutineArg() {
     for (auto i = CallSites.begin(), e = CallSites.end(); i != e; ++i)
       delete *i;
   }
+  SubroutineArg() = delete;
+  SubroutineArg(const SubroutineArg &) = delete;
+  SubroutineArg &operator=(const SubroutineArg &) = delete;
+
+  SubroutineArg(SubroutineArg &&) = default;
+  SubroutineArg &operator=(SubroutineArg &&) = delete;
+
   Indirectability checkIndirectability();
   ArgIndCallSite *createCallSite(CallInst *CI);
   Alignment getIndirectAlignment(unsigned GRFWidth) const;
@@ -496,7 +503,7 @@ static Value *searchForArg(Value *V) {
 std::vector<GenXArgIndirection::ArgToConvertAddr>
 GenXArgIndirection::collectAlreadyIndirected(LiveRange *ArgLR) {
   std::vector<GenXArgIndirection::ArgToConvertAddr> IndirectedArgInfo;
-  for (auto VI : ArgLR->getValues()) {
+  for (auto &VI : ArgLR->getValues()) {
     Value *Base = VI.getValue();
     std::vector<Value *> Addrs = Liveness->getAddressWithBase(Base);
     // Not a base
@@ -638,7 +645,7 @@ bool GenXArgIndirection::processArgLR(LiveRange *ArgLR)
     ArgToAddressArg.insert(SubrArg->addAddressArg());
   // Since the ArgLR has been set to NONE category, it cannot be used as a base
   // register and the indirected argument address should be used instead.
-  for (auto Info : IndirectedArgInfo) {
+  for (auto &Info : IndirectedArgInfo) {
     IGC_ASSERT_MESSAGE(ArgToAddressArg.count(Info.Arg),
                        "Cannot find indirected arg");
     Liveness->setArgAddressBase(Info.ConvertAddr, ArgToAddressArg[Info.Arg]);

IGC/VectorCompiler/lib/GenXCodeGen/GenXBaling.cpp

@@ -1439,7 +1439,7 @@ void GenXBaling::processMainInst(Instruction *Inst, int IntrinID) {
     // For an intrinsic, check the arg info of each arg to see if we can
     // bale into it.
     GenXIntrinsicInfo Info(IntrinID);
-    for (auto AI : Info.getInstDesc()) {
+    for (auto &AI : Info.getInstDesc()) {
       if (AI.isArgOrRet() && !AI.isRet()) {
         unsigned ArgIdx = AI.getArgIdx();
         switch (AI.getCategory()) {

IGC/VectorCompiler/lib/GenXCodeGen/GenXCFSimplification.cpp

@@ -284,8 +284,9 @@ BasicBlock *GenXCFSimplification::processBranchedOverBlock(BasicBlock *BB)
       Value *V = Phi->getIncomingValueForBlock(BB);
       replaceAndRecursivelySimplify(Phi, V);
     } else {
-      unsigned PredIdx = Phi->getBasicBlockIndex(Pred);
-      unsigned BBIdx = Phi->getBasicBlockIndex(BB);
+      auto PredIdx = Phi->getBasicBlockIndex(Pred);
+      auto BBIdx = Phi->getBasicBlockIndex(BB);
+      IGC_ASSERT_EXIT(PredIdx >= 0 && BBIdx >= 0);
       Phi->setIncomingValue(PredIdx, Phi->getIncomingValue(BBIdx));
       Phi->removeIncomingValue(BBIdx);
     }

IGC/VectorCompiler/lib/GenXCodeGen/GenXCategory.cpp

@@ -302,7 +302,9 @@ namespace {
     vc::RegCategory MostUsedCat_;
 
   public:
-    UsesCatInfo() : Uses_(), Mask_(0), MaxAlign_(0) {}
+    UsesCatInfo()
+        : Uses_(), Mask_(0), MaxAlign_(0), MostUsedCat_(vc::RegCategory::None) {
+    }
 
     UsesCatInfo(const GenXCategory &PassInfo, Value *V) : UsesCatInfo() {
       std::array<int, vc::numRegCategories()> Stat = {0};
@@ -667,7 +669,7 @@ bool GenXCategory::processValue(Value *V)
 
   Liveness->getOrCreateLiveRange(V, DefInfo.Cat, std::max(DefInfo.Align, UsesInfo.getMaxAlign()));
   auto Convs = buildConversions(V, DefInfo, UsesInfo);
-  for (auto UseInfo : UsesInfo.getUses()) {
+  for (auto &UseInfo : UsesInfo.getUses()) {
     if (UseInfo.Cat != DefInfo.Cat && UseInfo.Cat != vc::RegCategory::None) {
       Instruction *Conv;
       if (UseInfo.Cat == vc::RegCategory::Address) {

IGC/VectorCompiler/lib/GenXCodeGen/GenXCisaBuilder.cpp

@@ -556,7 +556,7 @@ class GenXKernelBuilder {
   Function *Func = nullptr;
   // function corresponding to VISAKernel currently being written
   Function *KernFunc = nullptr;
-  PreDefined_Surface StackSurf;
+  PreDefined_Surface StackSurf = PreDefined_Surface::PREDEFINED_SURFACE_INVALID;
 
   std::map<Function *, VISA_GenVar *> FPMap;
   SmallVector<InsertValueInst *, 10> RetvInserts;
@@ -944,6 +944,8 @@ class GenXKernelBuilder {
     collectKernelInfo();
   }
   ~GenXKernelBuilder() { clearLoops(); }
+  GenXKernelBuilder(const GenXKernelBuilder &) = delete;
+  GenXKernelBuilder &operator=(const GenXKernelBuilder &) = delete;
   void clearLoops() {
     for (auto i = Loops.begin(), e = Loops.end(); i != e; ++i) {
       delete i->second;
@@ -1627,11 +1629,11 @@ void GenXKernelBuilder::buildInstructions() {
                 auto Phi = dyn_cast<PHINode>(&*si);
                 if (!Phi)
                   break;
-                IGC_ASSERT_EXIT(Phi->getBasicBlockIndex(BB) >= 0);
+                auto PredIdx = Phi->getBasicBlockIndex(BB);
+                IGC_ASSERT_EXIT(PredIdx >= 0);
                 if (Phi->getType()->getPrimitiveSizeInBits() >=
                         (GrfByteSize * 8) * 4 &&
-                    isa<UndefValue>(
-                        Phi->getIncomingValue(Phi->getBasicBlockIndex(BB))))
+                    isa<UndefValue>(Phi->getIncomingValue(PredIdx)))
                   addLifetimeStartInst(Phi);
               }
             }
@@ -5043,6 +5045,7 @@ void GenXKernelBuilder::buildConvertAddr(CallInst *CI, genx::BaleInfo BI,
                    CI);
     }
   } else {
+    IGC_ASSERT_EXIT(GrfByteSize > 0);
     uint8_t rowOffset = Offset >> genx::log2(GrfByteSize);
     uint8_t colOffset = (Offset & (GrfByteSize - 1)) >> Log2_32(ElementBytes);
     auto TypeSize = BaseReg->Ty->getScalarType()->getPrimitiveSizeInBits() >> 3;

IGC/VectorCompiler/lib/GenXCodeGen/GenXCoalescing.cpp

@@ -1087,7 +1087,7 @@ void GenXCoalescing::processPhiNodes(FunctionGroup *FG)
   // Perform copy of uncoalesced phi node incomings.
   // New phis can be created during this, store them.
   std::vector<PHINode *> NewPhis;
-  for (auto Elem : PhiCopies) {
+  for (auto &Elem : PhiCopies) {
     processPhiCopy(Elem.Phi, Elem.IncomingIdx, NewPhis);
   }
   // Phi copies are resolved. Clean the list.
@@ -1107,7 +1107,7 @@ void GenXCoalescing::processPhiNodes(FunctionGroup *FG)
     NewPhis.clear();
 
     // Perform copy of uncoalesced phi node incomings.
-    for (auto Elem : PhiCopies) {
+    for (auto &Elem : PhiCopies) {
       processPhiCopy(Elem.Phi, Elem.IncomingIdx, NewPhis);
     }
     // Phi copies are resolved. Clean the list.
@@ -1899,9 +1899,9 @@ void GenXCoalescing::applyCopiesOptimized() {
   // it is still simple linear traverse through all copies.
 
   // Traverse all LRs
-  for (auto LRDataIt : SortedCD.CopiesPerLR) {
+  for (auto &LRDataIt : SortedCD.CopiesPerLR) {
     // Traverse all copy values
-    for (auto CDIt : LRDataIt.second.CopiesPerValue) {
+    for (auto &CDIt : LRDataIt.second.CopiesPerValue) {
       // Finally we got into current copy candidates.
       // Traverse all copy data.
       applyCopiesForValue(CDIt.second);