[Autobackout][FuncReg]Revert of change: 2ebc958

 Remove DispatchOCLWGInLinearOrder flag.

The DispatchOCLWGInLinearOrder flag is no longer needed because the workgroup vectorization order is fixed.

Author: ppogotov

IGC/Compiler/CISACodeGen/WIAnalysis.cpp

@@ -521,7 +521,9 @@ void WIAnalysisRunner::updateArgsDependency(llvm::Function* pF)
     //    order (intel_reqd_workgroup_walk_order()) and work group size (reqd_work_group_size()),
     //    we may derive that some of local IDs are uniform.
     bool localX_uniform = false, localY_uniform = false, localZ_uniform = false;
-    if (!IsSubroutine)
+    // DispatchOCLWGInLinearOrder should be removed after testing the guarded code.
+    if (!IsSubroutine &&
+        IGC_IS_FLAG_ENABLED(DispatchOCLWGInLinearOrder))
     {
         checkLocalIdUniform(pF, localX_uniform, localY_uniform, localZ_uniform);
     }
@@ -2150,8 +2152,8 @@ void WIAnalysisRunner::checkLocalIdUniform(
         IsLzUniform = true;
     }
 
-
-    if (WO_0 == 0 && WO_1 == 1 && WO_2 == 2)
+    if (IGC_IS_FLAG_ENABLED(DispatchOCLWGInLinearOrder) ||
+        (WO_0 == 0 && WO_1 == 1 && WO_2 == 2))
     {
         // linear order dispatch
         uint32_t XxY = X * Y;

IGC/Compiler/Optimizer/CodeAssumption.cpp

@@ -78,7 +78,8 @@ void CodeAssumption::uniformHelper(Module* M)
             auto BB = CI->getParent();
             auto KF = BB->getParent();
 
-            if (!IsSGIdUniform(m_pMDUtils, modMD, KF))
+            if (!IGC_IS_FLAG_ENABLED(DispatchOCLWGInLinearOrder) &&
+                !IsSGIdUniform(m_pMDUtils, modMD, KF))
                 continue;
 
             // The value must be uniform. Using shuffle with index=0 to

IGC/Compiler/tests/LowerGEPForPrivMem/i8_alloca_limit.ll

@@ -22,6 +22,9 @@ define spir_kernel void @WaveletDenoise(<4 x i8> addrspace(1)* %srcImage, <4 x i
 ; CHECK-DG1-NEXT:  entry:
 ; CHECK-DG1-NEXT:    [[I:%.*]] = extractelement <3 x i32> [[LOCALSIZE:%.*]], i64 0
 ; CHECK-DG1-NEXT:    [[TMP0:%.*]] = alloca <64 x i8>
+; CHECK-DG1-NEXT:    [[TMP:%.*]] = alloca [16 x float]
+; CHECK-DG1-NEXT:    [[TMP1:%.*]] = alloca <16 x float>
+; CHECK-DG1:         [[ARRAYIDX165_1:%.*]] = getelementptr inbounds [16 x float], [16 x float]* [[TMP]]
 ;
 ; CHECK-DG2-LABEL: @WaveletDenoise(
 ; CHECK-DG2-NEXT:  entry:

IGC/Compiler/tests/WIAnalysis/local_id.ll

@@ -261,6 +261,11 @@ DECLARE_IGC_REGKEY(bool, DisableDynamicTextureFolding,  false,  "Disable Dynamic
 DECLARE_IGC_REGKEY(bool, DisableDynamicResInfoFolding,  true,  "Disable Dynamic ResInfo Instruction Folding", false)
 DECLARE_IGC_REGKEY(bool, DisableRectListOpt,            false, "Disable Rect List optimization", false)
 
+DECLARE_IGC_REGKEY(bool, DispatchOCLWGInLinearOrder,    false, "If set, dispatch HW threads based on the linearized order of WI in a WG; \
+                                                                ie, let localSize=(lx, ly, lz), localId=(ix, iy, iz). And \
+                                                                   linearLocalId = ix + lx * (iy + ly * iz); \
+                                                                And linear order means that \
+                                                                   linearLocalId(lane[x+1])=linearLocalId(lane[x])+1", false)
 DECLARE_IGC_REGKEY(DWORD, EnableCodeAssumption,         1, \
     "If set (> 0), generate llvm.assume to help certain optimizations. It is OCL only for now. \
      Only 1 and 2 are valid. 2 will be 1 plus additional assumption. It also does other minor changes.", false)

IGC/common/igc_flags.h

@@ -187,6 +187,7 @@ $ export IGC_ShaderDumpEnable=1
 | `DisableUniformAnalysis` | Setting this to 1/true adds a compiler switch to disable uniform_analysis | - |
 | `DisableUniformTypedAccess` | Setting this will disable uniform typed access handling | - |
 | `DisableUniformURBWrite` | Disables generation of uniform URB write messages | - |
+| `DispatchOCLWGInLinearOrder` | If set, dispatch HW threads based on the linearized order of WI in a WG;<br/>                                                                ie, let localSize=(lx, ly, lz), localId=(ix, iy, iz). And<br/>                                                                   linearLocalId = ix + lx * (iy + ly * iz);<br/>                                                                And linear order means that<br/>                                                                   linearLocalId(lane[x+1])=linearLocalId(lane[x])+1 | - |
 | `EnableAtomicBranch` | Enable Atomic branch optimization which break atomic into if/else with atomic and read based on the operation | - |
 | `EnableBitcastedLoadNarrowing` | Enable narrowing of vector loads in bitcasts patterns. | - |
 | `EnableBitcastedLoadNarrowingToScalar` | Enable narrowing of vector loads to scalar ones in bitcasts patterns. | - |