Add regkey to control loosenSimd32occu result

- Regkey ForceLoosenSimd32Occu default 2 to use platform specific
  implementation. Value 0 & 1 will force the value.

Author: iwwu

IGC/Compiler/CISACodeGen/Platform.hpp

@@ -667,7 +667,10 @@ bool supportDynamicBTIsAllocation() const
 
 bool loosenSimd32occu() const
 {
-    return (m_platformInfo.eRenderCoreFamily >= IGFX_GEN12_CORE && m_platformInfo.eProductFamily != IGFX_DG2);
+    if (IGC_GET_FLAG_VALUE(ForceLoosenSimd32Occu) == 2)
+        return (m_platformInfo.eRenderCoreFamily >= IGFX_GEN12_CORE && m_platformInfo.eProductFamily != IGFX_DG2);
+    else
+        return IGC_GET_FLAG_VALUE(ForceLoosenSimd32Occu);
 }
 
 // Local memory here refers to memory on the device- e.g. HBM for PVC.

IGC/common/MDFrameWork.h

@@ -439,6 +439,7 @@ namespace IGC
         bool DisableFDivToFMulInvOpt                    = false;
         bool initializePhiSampleSourceWA                = false;
         bool WaDisableSubspanUseNoMaskForCB             = false;
+        bool DisableLoosenSimd32Occu                    = false;
 
         unsigned FastestS1Options                       = 0;  // FCEXP_NO_EXPRIMENT. Can't access the enum here for some reason.
     };

IGC/common/igc_flags.h

@@ -329,13 +329,14 @@ DECLARE_IGC_REGKEY(bool, ForceStatelessForQueueT,       true,  "In OCL, force to
 DECLARE_IGC_REGKEY(bool, ForceMemoryFenceBeforeEOT,     false, "Forces inserting SLM or gloabal memory fence before EOT if shader writes to SLM or goblam memory respectively.", false)
 DECLARE_IGC_REGKEY(bool, EnableRTmaskPso,               true,  "Enable render target mask optimization in PSO opt", false)
 DECLARE_IGC_REGKEY(DWORD, MSAAClearedKernel,            0,     "Insert the discard code for MSAA_MSC_Cleared kernels. 2/4/8/16", false)
-DECLARE_IGC_REGKEY(bool, EnablerReadSuppressionWA,    true, "Enable read suppression WA for the send and indirect access", false)
-DECLARE_IGC_REGKEY(bool, EnableLSCFenceUGMBeforeEOT,    true, "Enable inserting fence.ugm.06.tile before EOT if a kernel has any write to UGM [XeHPC, PVC].", true)
-DECLARE_IGC_REGKEY(bool, EnableRTLSCFenceUGMBeforeEOT,  true, "[tmp]Enable inserting fence.ugm.06.tile before EOT for RT shader [XeHPC, PVC].", false)
-DECLARE_IGC_REGKEY(bool, manualEnableRSWA,    false, "Enable read suppression WA for the send and indirect access", false)
-DECLARE_IGC_REGKEY(bool, DPASReadSuppressionWA,    true, "Enable read suppression WA for the send and indirect access", false)
-DECLARE_IGC_REGKEY(bool, EnableDivergentBarrierCheck,   false,  "Uses WIAnalysis to find barriers in divergent flow control. May have false positives.", false)
+DECLARE_IGC_REGKEY(bool, EnablerReadSuppressionWA,      true,  "Enable read suppression WA for the send and indirect access", false)
+DECLARE_IGC_REGKEY(bool, EnableLSCFenceUGMBeforeEOT,    true,  "Enable inserting fence.ugm.06.tile before EOT if a kernel has any write to UGM [XeHPC, PVC].", true)
+DECLARE_IGC_REGKEY(bool, EnableRTLSCFenceUGMBeforeEOT,  true,  "[tmp]Enable inserting fence.ugm.06.tile before EOT for RT shader [XeHPC, PVC].", false)
+DECLARE_IGC_REGKEY(bool, manualEnableRSWA,              false, "Enable read suppression WA for the send and indirect access", false)
+DECLARE_IGC_REGKEY(bool, DPASReadSuppressionWA,         true,  "Enable read suppression WA for the send and indirect access", false)
+DECLARE_IGC_REGKEY(bool, EnableDivergentBarrierCheck,   false, "Uses WIAnalysis to find barriers in divergent flow control. May have false positives.", false)
 DECLARE_IGC_REGKEY(bool, EnableBitcastExtractInsertPattern,   true,  "Enable BitcastExtractInsertPattern in CustomSafeOptPass.", true)
+DECLARE_IGC_REGKEY(DWORD, ForceLoosenSimd32Occu,        2,     "Control loosenSimd32occu return value. 0 - off, 1 - on, 2 - platform default", false)
 
 DECLARE_IGC_GROUP("Shader dumping")
 DECLARE_IGC_REGKEY(bool, EnableCosDump, false, "Enable cos dump", true)