Replace zero dpas accumulator argument with null register in VC

DPAS instruction interpret null-register accumulator input (src0) as
zero value. So, the compiler don't need to emit extra MOV instructions
to initialize the DPAS accumulator registers.

Author: vmustya

IGC/VectorCompiler/lib/GenXCodeGen/GenXPatternMatch.cpp

@@ -1,6 +1,6 @@
 /*========================== begin_copyright_notice ============================
 
-Copyright (C) 2017-2023 Intel Corporation
+Copyright (C) 2017-2024 Intel Corporation
 
 SPDX-License-Identifier: MIT
 
@@ -198,6 +198,7 @@ class GenXPatternMatch : public FunctionPass,
   bool simplifyCmp(CmpInst *Cmp);
   CmpInst *reduceCmpWidth(CmpInst *Cmp);
   bool simplifyNullDst(CallInst *Inst);
+  bool simplifyDpasNullSrc(CallInst *Inst);
   // Transform logic operation with a mask from <N x iM> to <N/(32/M) x i32>
   bool extendMask(BinaryOperator *BO);
   bool mergeApply(CallInst *CI);
@@ -523,11 +524,20 @@ void GenXPatternMatch::visitBinaryOperator(BinaryOperator &I) {
 }
 
 void GenXPatternMatch::visitCallInst(CallInst &I) {
-  if (Kind == PatternMatchKind::PostLegalization) {
-    return;
+  auto IID = vc::getAnyIntrinsicID(&I);
+
+  switch (IID) {
+  default:
+    break;
+  case GenXIntrinsic::genx_dpas:
+  case GenXIntrinsic::genx_dpas2:
+    Changed |= simplifyDpasNullSrc(&I);
+    break;
   }
 
-  auto IID = vc::getAnyIntrinsicID(&I);
+  if (Kind == PatternMatchKind::PostLegalization)
+    return;
+
   switch (IID) {
   default:
     break;
@@ -3719,6 +3729,47 @@ bool GenXPatternMatch::simplifyNullDst(CallInst *Inst) {
   return false;
 }
 
+bool GenXPatternMatch::simplifyDpasNullSrc(CallInst *Inst) {
+  auto IID = vc::getAnyIntrinsicID(Inst);
+  IGC_ASSERT_EXIT(IID == GenXIntrinsic::genx_dpas ||
+                  IID == GenXIntrinsic::genx_dpas2);
+
+  auto *Acc = dyn_cast<Constant>(Inst->getArgOperand(0));
+  if (!Acc || !Acc->isZeroValue())
+    return false;
+
+  IRBuilder<> Builder(Inst);
+
+  // Accumulator input is constant zero, so we could use dpas_nosrc0 intrinsic
+  auto *Src1 = Inst->getArgOperand(1);
+  auto *Src2 = Inst->getArgOperand(2);
+
+  Value *Desc = Inst->getArgOperand(3);
+  if (IID == GenXIntrinsic::genx_dpas2) {
+    auto Src1Precision =
+        cast<ConstantInt>(Inst->getArgOperand(3))->getZExtValue() & 0xff;
+    auto Src2Precision =
+        cast<ConstantInt>(Inst->getArgOperand(4))->getZExtValue() & 0xff;
+    auto SystolicDepth =
+        cast<ConstantInt>(Inst->getArgOperand(5))->getZExtValue() & 0xff;
+    auto RepeatCount =
+        cast<ConstantInt>(Inst->getArgOperand(6))->getZExtValue() & 0xff;
+
+    Desc = Builder.getInt32(Src1Precision | Src2Precision << 8 |
+                            SystolicDepth << 16 | RepeatCount << 24);
+  }
+
+  auto *Func = vc::getAnyDeclaration(
+      Inst->getModule(), GenXIntrinsic::genx_dpas_nosrc0,
+      {Inst->getType(), Src1->getType(), Src2->getType()});
+  auto *NewCI = Builder.CreateCall(Func, {Src1, Src2, Desc});
+  NewCI->takeName(Inst);
+  Inst->replaceAllUsesWith(NewCI);
+  Inst->eraseFromParent();
+
+  return true;
+}
+
 bool canExtendMask(BinaryOperator *BO) {
   Type *InstTy = BO->getType();
   auto Op0 = dyn_cast<ConstantDataVector>(BO->getOperand(0));

IGC/VectorCompiler/test/PatternMatch/dpas-zero-acc.ll

@@ -0,0 +1,26 @@
+;=========================== begin_copyright_notice ============================
+;
+; Copyright (C) 2024 Intel Corporation
+;
+; SPDX-License-Identifier: MIT
+;
+;============================ end_copyright_notice =============================
+
+; RUN: %opt %use_old_pass_manager% -GenXPatternMatch -march=genx64 -mcpu=XeHPC -mtriple=spir64-unknown-unknown -S < %s | FileCheck %s
+
+declare <16 x i32> @llvm.genx.dpas.v16i32.v16i32.v128i32.v8i32(<16 x i32>, <128 x i32>, <8 x i32>, i32)
+declare <16 x i32> @llvm.genx.dpas2.v16i32.v16i32.v128i32.v8i32(<16 x i32>, <128 x i32>, <8 x i32>, i32, i32, i32, i32, i32, i32)
+
+; CHECK-LABEL: @dpas(
+define <16 x i32> @dpas(<128 x i32> %src1, <8 x i32> %src2) {
+  ; CHECK: %res = call <16 x i32> @llvm.genx.dpas.nosrc0.v16i32.v128i32.v8i32(<128 x i32> %src1, <8 x i32> %src2, i32 17303560)
+  %res = call <16 x i32> @llvm.genx.dpas.v16i32.v16i32.v128i32.v8i32(<16 x i32> zeroinitializer, <128 x i32> %src1, <8 x i32> %src2, i32 17303560)
+  ret <16 x i32> %res
+}
+
+; CHECK-LABEL: @dpas2(
+define <16 x i32> @dpas2(<128 x i32> %src1, <8 x i32> %src2) {
+  ; CHECK: %res = call <16 x i32> @llvm.genx.dpas.nosrc0.v16i32.v128i32.v8i32(<128 x i32> %src1, <8 x i32> %src2, i32 17303560)
+  %res = call <16 x i32> @llvm.genx.dpas2.v16i32.v16i32.v128i32.v8i32(<16 x i32> zeroinitializer, <128 x i32> %src1, <8 x i32> %src2, i32 8, i32 8, i32 8, i32 1, i32 1, i32 1)
+  ret <16 x i32> %res
+}