Skip to content

Commit f9db7a4

Browse files
pratikasharigcbot
authored andcommitted
[Autobackout][FuncReg]Revert of change: 7f78aef
Decide emission of pre-fill for spills based on presence of corresponding pseudo kill or def count of spill.
1 parent 172c6d2 commit f9db7a4

File tree

2 files changed

+4
-155
lines changed

2 files changed

+4
-155
lines changed

visa/SpillManagerGMRF.cpp

Lines changed: 4 additions & 148 deletions
Original file line numberDiff line numberDiff line change
@@ -2804,103 +2804,9 @@ void SpillManagerGRF::insertSpillRangeCode(
28042804
return;
28052805
}
28062806

2807-
auto IsUniqueDef = [this, inst, bb, spillDcl]()
2808-
{
2809-
// return true if spilled variable has a single def
2810-
// and it is not live-in to current bb (eg, loop, sub).
2811-
if (VarDefs[spillDcl].size() != 1)
2812-
{
2813-
// check whether multiple defs exist in program for current
2814-
// lb, rb
2815-
auto lb = inst->getDst()->getLeftBound();
2816-
auto rb = inst->getDst()->getRightBound();
2817-
unsigned int count = 0;
2818-
auto& defs = VarDefs[spillDcl];
2819-
for (auto& def : defs)
2820-
{
2821-
if (def.first <= rb &&
2822-
def.second >= lb)
2823-
++count;
2824-
}
2825-
2826-
if(count > 1)
2827-
return false;
2828-
}
2829-
2830-
// check whether variable is live-in to BB
2831-
if (lvInfo_->isLiveAtEntry(bb, spillDcl->getRegVar()->getId()))
2832-
return false;
2833-
2834-
return true;
2835-
};
2836-
2837-
auto PseudoKillFound = [spilledInstIter, bb, spillDcl]()
2838-
{
2839-
// Search upwards from spilledInstIter to find a pseudo kill.
2840-
// Return true if one is found, false otherwise.
2841-
// When a pseudo kill is found, it means read-modify-write is
2842-
// not needed.
2843-
auto bbBegin = bb->begin();
2844-
if (spilledInstIter == bbBegin)
2845-
return false;
2846-
auto it = spilledInstIter;
2847-
--it;
2848-
while (it != bbBegin)
2849-
{
2850-
auto inst = *it;
2851-
// check if adjacent instruction is a pseudo kill
2852-
if (inst->isPseudoKill())
2853-
{
2854-
if (inst->getDst()->getTopDcl() == spillDcl)
2855-
return true;
2856-
}
2857-
else
2858-
{
2859-
auto dst = inst->getDst();
2860-
if (!dst)
2861-
return false;
2862-
2863-
// recognize pattern where V10 is spilled:
2864-
// pseudo_kill V10
2865-
// op (8) V10(0,0) ...
2866-
// op (8) V10(2,0) ... <-- Current inst
2867-
//
2868-
// becomes:
2869-
// pseudo_kill V10
2870-
// op (8) SP_V10(0,0) ... [2]
2871-
// intrinsic_spill (8) ... SP_V10 ... [1]
2872-
// op (8) V10(2,0) <-- Current inst
2873-
if (inst->isSpillIntrinsic() &&
2874-
inst->asSpillIntrinsic()->getPayload() &&
2875-
inst->asSpillIntrinsic()->getPayload()->getTopDcl()->getRegVar()->isRegVarTransient())
2876-
{
2877-
auto spillBase = ((G4_RegVarTransient*)inst->asSpillIntrinsic()->getPayload()->getTopDcl()->getRegVar())->getAbsBaseRegVar();
2878-
if (spillBase->getDeclare()->getRootDeclare() != spillDcl)
2879-
return false;
2880-
// Fall through for instruction [1] above
2881-
}
2882-
else if (dst &&
2883-
dst->getTopDcl() &&
2884-
dst->getTopDcl()->getRegVar()->isRegVarTransient())
2885-
{
2886-
auto spillBase = ((G4_RegVarTransient*)dst->getTopDcl()->getRegVar())->getAbsBaseRegVar();
2887-
if (spillBase->getDeclare()->getRootDeclare() != spillDcl)
2888-
return false;
2889-
// Fall through for instruction [2] above
2890-
}
2891-
else if(inst->getDst()->getTopDcl() != spillDcl)
2892-
return false;
2893-
}
2894-
--it;
2895-
}
2896-
return false;
2897-
};
2898-
28992807
//subreg offset for new dst that replaces the spilled dst
29002808
auto newSubregOff = 0;
29012809

2902-
auto pseudoKillFound = PseudoKillFound();
2903-
auto isUniqueDef = IsUniqueDef();
29042810
if (inst->mayExceedTwoGRF())
29052811
{
29062812
// Handle send instructions (special treatment)
@@ -2915,9 +2821,7 @@ void SpillManagerGRF::insertSpillRangeCode(
29152821
createAndInitMHeader (
29162822
(G4_RegVarTransient *) spillRangeDcl->getRegVar());
29172823

2918-
bool needRMW = !pseudoKillFound &&
2919-
!isUniqueDef &&
2920-
inst->isPartialWriteForSpill(!bb->isAllLaneActive());
2824+
bool needRMW = inst->isPartialWriteForSpill(!bb->isAllLaneActive());
29212825
if (needRMW)
29222826
{
29232827
sendInSpilledRegVarPortions(
@@ -2952,9 +2856,7 @@ void SpillManagerGRF::insertSpillRangeCode(
29522856

29532857
// Unaligned region specific handling.
29542858
unsigned int spillSendOption = InstOpt_WriteEnable;
2955-
if (!pseudoKillFound &&
2956-
!isUniqueDef &&
2957-
shouldPreloadSpillRange(*spilledInstIter, bb)) {
2859+
if (shouldPreloadSpillRange(*spilledInstIter, bb)) {
29582860

29592861
// Preload the segment aligned spill range from memory to use
29602862
// as an overlay
@@ -3036,13 +2938,7 @@ void SpillManagerGRF::insertSpillRangeCode(
30362938
newSubregOff = spilledRegion->getSubRegOff();
30372939
if (!bb->isAllLaneActive())
30382940
{
3039-
if (!pseudoKillFound &&
3040-
!isUniqueDef)
3041-
{
3042-
// If either pseudo kill is found or if the range is a unique def,
3043-
// use WriteEnable option in spill.
3044-
spillSendOption = (*spilledInstIter)->getMaskOption();
3045-
}
2941+
spillSendOption = (*spilledInstIter)->getMaskOption();
30462942
}
30472943
}
30482944

@@ -3977,33 +3873,6 @@ void SpillManagerGRF::runSpillAnalysis()
39773873
}
39783874
}
39793875

3980-
void SpillManagerGRF::populateDefsTable()
3981-
{
3982-
for (auto bb : gra.kernel.fg)
3983-
{
3984-
for (auto inst : *bb)
3985-
{
3986-
if (inst->isPseudoKill())
3987-
continue;
3988-
3989-
auto dst = inst->getDst();
3990-
3991-
if (dst && !dst->isNullReg())
3992-
{
3993-
auto topdcl = dst->getTopDcl();
3994-
3995-
if (topdcl)
3996-
{
3997-
auto lb = dst->getLeftBound();
3998-
auto rb = dst->getRightBound();
3999-
VarDefs[topdcl].push_back(std::make_pair(lb, rb));
4000-
}
4001-
}
4002-
}
4003-
}
4004-
}
4005-
4006-
40073876
// Insert spill/fill code for all registers that have not been assigned
40083877
// physical registers in the current iteration of the graph coloring
40093878
// allocator.
@@ -4044,9 +3913,6 @@ bool SpillManagerGRF::insertSpillFillCode (
40443913
return false;
40453914
}
40463915

4047-
// Populate def table as it helps us decide whether read-modify-write is needed
4048-
populateDefsTable();
4049-
40503916
// Insert spill/fill code for all basic blocks.
40513917

40523918
FlowGraph& fg = kernel->fg;
@@ -4055,7 +3921,6 @@ bool SpillManagerGRF::insertSpillFillCode (
40553921
{
40563922
bbId_ = (*it)->getId();
40573923
INST_LIST::iterator jt = (*it)->begin();
4058-
std::list<INST_LIST_ITER> pseudoKills;
40593924

40603925
while (jt != (*it)->end()) {
40613926
INST_LIST::iterator kt = jt;
@@ -4085,11 +3950,7 @@ bool SpillManagerGRF::insertSpillFillCode (
40853950
{
40863951
if (inst->isPseudoKill())
40873952
{
4088-
// This pseudo kill corresponds to a spilled variable, so
4089-
// it can be removed. But it is preserved till spill code
4090-
// is inserted for the variable as it provides a hint to
4091-
// spill insertion that read-modify-write is not needed.
4092-
pseudoKills.push_back(jt);
3953+
(*it)->erase(jt);
40933954
jt = kt;
40943955
continue;
40953956
}
@@ -4142,11 +4003,6 @@ bool SpillManagerGRF::insertSpillFillCode (
41424003

41434004
jt = kt;
41444005
}
4145-
4146-
for(auto killIt : pseudoKills)
4147-
{
4148-
(*it)->erase(killIt);
4149-
}
41504006
}
41514007

41524008
bbId_ = UINT_MAX;

visa/SpillManagerGMRF.h

Lines changed: 0 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -593,8 +593,6 @@ class SpillManagerGRF
593593
}
594594
}
595595

596-
void populateDefsTable();
597-
598596
// Data
599597
GlobalRA& gra;
600598
IR_Builder * builder_;
@@ -625,11 +623,6 @@ class SpillManagerGRF
625623
const Interference * spillIntf_;
626624
vISA::Mem_Manager mem_;
627625

628-
// Dcl -> vector[<lb, rb>]
629-
// this data structure helps check whether a definition or part of it
630-
// has multiple definitions in the program.
631-
std::unordered_map<G4_Declare*, std::vector<std::pair<unsigned int, unsigned int>>> VarDefs;
632-
633626
// The number of GRF spill.
634627
unsigned numGRFSpill = 0;
635628

0 commit comments

Comments
 (0)