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Commit 49c4977

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AlexeySachkovAlexeySachkov
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[SYCL][NFC] Modernize some tests to match SYCL 2020 (#1559)
- removed usage of `cl_*` types in favor of standard C++ types and/or `vec` aliases defined in SYCL 2020 spec. - prefixed some `cl_*` types with `opencl::` namespace
1 parent 3b9ed17 commit 49c4977

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7 files changed

+84
-84
lines changed

7 files changed

+84
-84
lines changed

‎SYCL/Basic/boolean.cpp

Lines changed: 23 additions & 23 deletions
Original file line numberDiff line numberDiff line change
@@ -17,9 +17,9 @@ d::Boolean<3> foo() {
1717

1818
int main() {
1919
{
20-
s::cl_long4 r{0};
20+
s::long4 r{0};
2121
{
22-
buffer<s::cl_long4, 1> BufR(&r, range<1>(1));
22+
buffer<s::long4, 1> BufR(&r, range<1>(1));
2323
queue myQueue;
2424
myQueue.submit([&](handler &cgh) {
2525
auto AccR = BufR.get_access<access::mode::write>(cgh);
@@ -29,10 +29,10 @@ int main() {
2929
});
3030
});
3131
}
32-
s::cl_long r1 = r.s0();
33-
s::cl_long r2 = r.s1();
34-
s::cl_long r3 = r.s2();
35-
s::cl_long r4 = r.s3();
32+
long long r1 = r.s0();
33+
long long r2 = r.s1();
34+
long long r3 = r.s2();
35+
long long r4 = r.s3();
3636

3737
std::cout << "r1 " << r1 << " r2 " << r2 << " r3 " << r3 << " r4 " << r4
3838
<< std::endl;
@@ -44,18 +44,18 @@ int main() {
4444
}
4545

4646
{
47-
s::cl_short3 r{0};
47+
s::short3 r{0};
4848
{
49-
buffer<s::cl_short3, 1> BufR(&r, range<1>(1));
49+
buffer<s::short3, 1> BufR(&r, range<1>(1));
5050
queue myQueue;
5151
myQueue.submit([&](handler &cgh) {
5252
auto AccR = BufR.get_access<access::mode::write>(cgh);
5353
cgh.single_task<class b3_sh3>([=]() { AccR[0] = foo(); });
5454
});
5555
}
56-
s::cl_short r1 = r.s0();
57-
s::cl_short r2 = r.s1();
58-
s::cl_short r3 = r.s2();
56+
short r1 = r.s0();
57+
short r2 = r.s1();
58+
short r3 = r.s2();
5959

6060
std::cout << "r1 " << r1 << " r2 " << r2 << " r3 " << r3 << std::endl;
6161

@@ -65,11 +65,11 @@ int main() {
6565
}
6666

6767
{
68-
s::cl_int r1[6];
69-
s::cl_int r2[6];
68+
int r1[6];
69+
int r2[6];
7070
{
71-
buffer<s::cl_int, 1> BufR1(r1, range<1>(6));
72-
buffer<s::cl_int, 1> BufR2(r2, range<1>(6));
71+
buffer<int, 1> BufR1(r1, range<1>(6));
72+
buffer<int, 1> BufR2(r2, range<1>(6));
7373
queue myQueue;
7474
myQueue.submit([&](handler &cgh) {
7575
auto AccR1 = BufR1.get_access<access::mode::write>(cgh);
@@ -117,14 +117,14 @@ int main() {
117117
}
118118

119119
{
120-
s::cl_int4 i4 = {1, -2, 0, -3};
120+
s::int4 i4 = {1, -2, 0, -3};
121121
d::Boolean<4> b4(i4);
122122
i4 = b4;
123123

124-
s::cl_int r1 = i4.s0();
125-
s::cl_int r2 = i4.s1();
126-
s::cl_int r3 = i4.s2();
127-
s::cl_int r4 = i4.s3();
124+
int r1 = i4.s0();
125+
int r2 = i4.s1();
126+
int r3 = i4.s2();
127+
int r4 = i4.s3();
128128

129129
std::cout << "r1 " << r1 << " r2 " << r2 << " r3 " << r3 << " r4 " << r4
130130
<< std::endl;
@@ -135,9 +135,9 @@ int main() {
135135
}
136136

137137
{
138-
s::cl_int r1 = d::Boolean<1>(s::cl_int{-1});
139-
s::cl_int r2 = d::Boolean<1>(s::cl_int{0});
140-
s::cl_int r3 = d::Boolean<1>(s::cl_int{1});
138+
int r1 = d::Boolean<1>(int{-1});
139+
int r2 = d::Boolean<1>(int{0});
140+
int r3 = d::Boolean<1>(int{1});
141141
std::cout << "r1 " << r1 << " r2 " << r2 << " r3 " << r3 << std::endl;
142142
assert(r1 == 1);
143143
assert(r2 == 0);

‎SYCL/Basic/built-ins.cpp

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -56,14 +56,14 @@ int main() {
5656

5757
// Test common
5858
{
59-
s::buffer<s::cl_float, 1> BufMin(s::range<1>(1));
60-
s::buffer<s::cl_float2, 1> BufMax(s::range<1>(1));
59+
s::buffer<float, 1> BufMin(s::range<1>(1));
60+
s::buffer<s::float2, 1> BufMax(s::range<1>(1));
6161
q.submit([&](s::handler &cgh) {
6262
auto AccMin = BufMin.get_access<s::access::mode::write>(cgh);
6363
auto AccMax = BufMax.get_access<s::access::mode::write>(cgh);
6464
cgh.single_task<class common>([=]() {
65-
AccMax[0] = s::max(s::cl_float2{0.5f, 2.5f}, s::cl_float2{2.3f, 2.3f});
66-
AccMin[0] = s::min(s::cl_float{0.5f}, s::cl_float{2.3f});
65+
AccMax[0] = s::max(s::float2{0.5f, 2.5f}, s::float2{2.3f, 2.3f});
66+
AccMin[0] = s::min(float{0.5f}, float{2.3f});
6767
});
6868
});
6969

‎SYCL/Basic/group_async_copy.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -161,7 +161,7 @@ int main() {
161161
return 1;
162162
if (test<vec<bool, 4>>(Stride))
163163
return 1;
164-
if (test<sycl::cl_bool>(Stride))
164+
if (test<sycl::opencl::cl_bool>(Stride))
165165
return 1;
166166
if (test<std::byte>(Stride))
167167
return 1;

‎SYCL/Basic/vector_operators.cpp

Lines changed: 37 additions & 37 deletions
Original file line numberDiff line numberDiff line change
@@ -43,7 +43,7 @@ int main() {
4343
/* Separate checks for NumElements=1 edge case */
4444

4545
{
46-
using vec_type = s::vec<s::cl_char, 1>;
46+
using vec_type = s::vec<char, 1>;
4747
vec_type res;
4848
{
4949
s::buffer<vec_type, 1> Buf(&res, s::range<1>(1));
@@ -63,15 +63,15 @@ int main() {
6363
}
6464

6565
{
66-
using vec_type = s::vec<s::cl_char, 1>;
66+
using vec_type = s::vec<char, 1>;
6767
vec_type res;
6868
{
6969
s::buffer<vec_type, 1> Buf(&res, s::range<1>(1));
7070
Queue.submit([&](s::handler &cgh) {
7171
auto Acc = Buf.get_access<s::access::mode::write>(cgh);
7272
cgh.single_task<class isequal_vec_op_1_elem_scalar>([=]() {
7373
vec_type vec(2);
74-
s::cl_char rhs_scalar = 2;
74+
char rhs_scalar = 2;
7575
Acc[0] = vec == rhs_scalar;
7676
});
7777
});
@@ -87,17 +87,17 @@ int main() {
8787

8888
// SYCL vec<>, SYCL vec<>
8989

90-
// Operator ==, cl_uint
90+
// Operator ==, unsigned int
9191
{
92-
using res_vec_type = s::vec<s::cl_int, 4>;
92+
using res_vec_type = s::int4;
9393
res_vec_type res;
9494
{
9595
s::buffer<res_vec_type, 1> Buf(&res, s::range<1>(1));
9696
Queue.submit([&](s::handler &cgh) {
9797
auto Acc = Buf.get_access<s::access::mode::write>(cgh);
9898
cgh.single_task<class isequal_vec_op>([=]() {
99-
s::vec<s::cl_uint, 4> vec1(42, 42, 42, 0);
100-
s::vec<s::cl_uint, 4> vec2(0, 42, 42, 0);
99+
s::uint4 vec1(42, 42, 42, 0);
100+
s::uint4 vec2(0, 42, 42, 0);
101101
Acc[0] = vec1 == vec2;
102102
});
103103
});
@@ -106,17 +106,17 @@ int main() {
106106
check_result_length_4<res_vec_type>(res, expected);
107107
}
108108

109-
// Operator <, cl_double
109+
// Operator <, double
110110
if (Queue.get_device().has(sycl::aspect::fp64)) {
111-
using res_vec_type = s::vec<s::cl_long, 4>;
111+
using res_vec_type = s::long4;
112112
res_vec_type res;
113113
{
114114
s::buffer<res_vec_type, 1> Buf(&res, s::range<1>(1));
115115
Queue.submit([&](s::handler &cgh) {
116116
auto Acc = Buf.get_access<s::access::mode::write>(cgh);
117117
cgh.single_task<class isless_vec_op>([=]() {
118-
s::vec<s::cl_double, 4> vec1(0.5, 10.1, 10.2, 10.3);
119-
s::vec<s::cl_double, 4> vec2(10.5, 0.1, 0.2, 0.3);
118+
s::double4 vec1(0.5, 10.1, 10.2, 10.3);
119+
s::double4 vec2(10.5, 0.1, 0.2, 0.3);
120120
Acc[0] = vec1 < vec2;
121121
});
122122
});
@@ -125,17 +125,17 @@ int main() {
125125
check_result_length_4<res_vec_type>(res, expected);
126126
}
127127

128-
// Operator >, cl_char
128+
// Operator >, char
129129
{
130-
using res_vec_type = s::vec<s::cl_char, 4>;
130+
using res_vec_type = s::char4;
131131
res_vec_type res;
132132
{
133133
s::buffer<res_vec_type, 1> Buf(&res, s::range<1>(1));
134134
Queue.submit([&](s::handler &cgh) {
135135
auto Acc = Buf.get_access<s::access::mode::write>(cgh);
136136
cgh.single_task<class isgreater_vec_op>([=]() {
137-
s::vec<s::cl_char, 4> vec1(0, 0, 42, 42);
138-
s::vec<s::cl_char, 4> vec2(42, 0, 0, -42);
137+
s::char4 vec1(0, 0, 42, 42);
138+
s::char4 vec2(42, 0, 0, -42);
139139
Acc[0] = vec1 > vec2;
140140
});
141141
});
@@ -144,17 +144,17 @@ int main() {
144144
check_result_length_4<res_vec_type>(res, expected);
145145
}
146146

147-
// Operator <=, cl_half
147+
// Operator <=, half
148148
if (Queue.get_device().has(sycl::aspect::fp16)) {
149-
using res_vec_type = s::vec<s::cl_short, 4>;
149+
using res_vec_type = s::short4;
150150
res_vec_type res;
151151
{
152152
s::buffer<res_vec_type, 1> Buf(&res, s::range<1>(1));
153153
Queue.submit([&](s::handler &cgh) {
154154
auto Acc = Buf.get_access<s::access::mode::write>(cgh);
155155
cgh.single_task<class isnotgreater_vec_op>([=]() {
156-
s::vec<s::cl_half, 4> vec1(0, 0, 42, 42);
157-
s::vec<s::cl_half, 4> vec2(42, 0, 0, -42);
156+
s::half4 vec1(0, 0, 42, 42);
157+
s::half4 vec2(42, 0, 0, -42);
158158
Acc[0] = vec1 <= vec2;
159159
});
160160
});
@@ -165,17 +165,17 @@ int main() {
165165

166166
// SYCL vec<>, OpenCL built-in
167167

168-
// Operator >=, cl_ulong
168+
// Operator >=, unsigned long
169169
{
170-
using res_vec_type = s::vec<s::cl_long, 4>;
170+
using res_vec_type = s::long4;
171171
res_vec_type res;
172172
{
173173
s::buffer<res_vec_type, 1> Buf(&res, s::range<1>(1));
174174
Queue.submit([&](s::handler &cgh) {
175175
auto Acc = Buf.get_access<s::access::mode::write>(cgh);
176176
cgh.single_task<class isnotless_vec_op>([=]() {
177-
s::vec<s::cl_ulong, 4> vec1(0, 0, 42, 42);
178-
s::cl_ulong4 vec2{42, 0, 0, 0};
177+
s::ulong4 vec1(0, 0, 42, 42);
178+
s::ulong4 vec2{42, 0, 0, 0};
179179
Acc[0] = vec1 >= vec2;
180180
});
181181
});
@@ -184,17 +184,17 @@ int main() {
184184
check_result_length_4<res_vec_type>(res, expected);
185185
}
186186

187-
// Operator !=, cl_ushort
187+
// Operator !=, unsigned short
188188
{
189-
using res_vec_type = s::vec<s::cl_short, 4>;
189+
using res_vec_type = s::short4;
190190
res_vec_type res;
191191
{
192192
s::buffer<res_vec_type, 1> Buf(&res, s::range<1>(1));
193193
Queue.submit([&](s::handler &cgh) {
194194
auto Acc = Buf.get_access<s::access::mode::write>(cgh);
195195
cgh.single_task<class isnotequal_vec_op>([=]() {
196-
s::vec<s::cl_ushort, 4> vec1(0, 0, 42, 42);
197-
s::cl_ushort4 vec2{42, 0, 0, 42};
196+
s::ushort4 vec1(0, 0, 42, 42);
197+
s::ushort4 vec2{42, 0, 0, 42};
198198
Acc[0] = vec1 != vec2;
199199
});
200200
});
@@ -203,17 +203,17 @@ int main() {
203203
check_result_length_4<res_vec_type>(res, expected);
204204
}
205205

206-
// Operator &&, cl_int
206+
// Operator &&, int
207207
{
208-
using res_vec_type = s::vec<s::cl_int, 4>;
208+
using res_vec_type = s::int4;
209209
res_vec_type res;
210210
{
211211
s::buffer<res_vec_type, 1> Buf(&res, s::range<1>(1));
212212
Queue.submit([&](s::handler &cgh) {
213213
auto Acc = Buf.get_access<s::access::mode::write>(cgh);
214214
cgh.single_task<class logical_and_vec_op>([=]() {
215-
s::vec<s::cl_int, 4> vec1(0, 0, 42, 42);
216-
s::cl_int4 vec2{42, 0, 0, 42};
215+
s::int4 vec1(0, 0, 42, 42);
216+
s::int4 vec2{42, 0, 0, 42};
217217
Acc[0] = vec1 && vec2;
218218
});
219219
});
@@ -222,17 +222,17 @@ int main() {
222222
check_result_length_4<res_vec_type>(res, expected);
223223
}
224224

225-
// Operator ||, cl_int
225+
// Operator ||, int
226226
{
227-
using res_vec_type = s::vec<s::cl_int, 4>;
227+
using res_vec_type = s::int4;
228228
res_vec_type res;
229229
{
230230
s::buffer<res_vec_type, 1> Buf(&res, s::range<1>(1));
231231
Queue.submit([&](s::handler &cgh) {
232232
auto Acc = Buf.get_access<s::access::mode::write>(cgh);
233233
cgh.single_task<class logical_or_vec_op>([=]() {
234-
s::vec<s::cl_int, 4> vec1(0, 0, 42, 42);
235-
s::cl_int4 vec2{42, 0, 0, 42};
234+
s::int4 vec1(0, 0, 42, 42);
235+
s::int4 vec2{42, 0, 0, 42};
236236
Acc[0] = vec1 || vec2;
237237
});
238238
});
@@ -244,14 +244,14 @@ int main() {
244244
// as() function.
245245
// reinterprets each element as a different datatype.
246246
{
247-
using res_vec_type = s::vec<s::cl_int, 4>;
247+
using res_vec_type = s::int4;
248248
res_vec_type res;
249249
{
250250
s::buffer<res_vec_type, 1> Buf(&res, s::range<1>(1));
251251
Queue.submit([&](s::handler &cgh) {
252252
auto Acc = Buf.get_access<s::access::mode::write>(cgh);
253253
cgh.single_task<class as_op>([=]() {
254-
s::vec<s::cl_float, 4> vec1(4.5f, 0, 3.5f, -10.0f);
254+
s::float4 vec1(4.5f, 0, 3.5f, -10.0f);
255255
Acc[0] = vec1.template as<res_vec_type>();
256256
});
257257
});

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